Searched refs:mmUVD_RB_WPTR (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_6_0_d.h | 48 #define mmUVD_RB_WPTR 0x3c2a macro
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| A D | uvd_7_0_offset.h | 102 #define mmUVD_RB_WPTR … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 224 #define mmUVD_RB_WPTR … macro
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| A D | vcn_2_5_offset.h | 559 #define mmUVD_RB_WPTR … macro
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| A D | vcn_2_0_0_offset.h | 936 #define mmUVD_RB_WPTR … macro
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| A D | vcn_3_0_0_offset.h | 889 #define mmUVD_RB_WPTR … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v1_0.c | 935 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1170 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_stop_dpg_mode()
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1604 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_enc_ring_get_wptr()
1621 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, in vcn_v1_0_enc_ring_set_wptr()
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| A D | vcn_v2_5.c | 1076 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1300 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v2_5_stop_dpg_mode()
1430 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1604 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v2_5_enc_ring_get_wptr()
1629 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
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| A D | vcn_v2_0.c | 1077 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1104 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v2_0_stop_dpg_mode()
1232 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1564 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v2_0_enc_ring_get_wptr()
1589 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
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| A D | uvd_v6_0.c | 126 return RREG32(mmUVD_RB_WPTR); in uvd_v6_0_enc_ring_get_wptr()
157 WREG32(mmUVD_RB_WPTR, in uvd_v6_0_enc_ring_set_wptr()
864 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
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| A D | vcn_v3_0.c | 1246 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1484 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v3_0_stop_dpg_mode()
1622 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1998 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v3_0_enc_ring_get_wptr()
2023 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
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| A D | uvd_v7_0.c | 123 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
161 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
1112 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
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