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Searched refs:mmUVD_SOFT_RESET (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Duvd_v3_1.c374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start()
376 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start()
378 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start()
398 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
495 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v3_1_stop()
A Duvd_v4_2.c332 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
334 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
336 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
353 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
356 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
453 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v4_2_stop()
A Duvd_v5_0.c340 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v5_0_start()
371 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
381 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
397 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
400 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
466 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_stop()
A Duvd_v7_0.c874 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
894 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
923 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); in uvd_v7_0_sriov_start()
988 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1024 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1037 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); in uvd_v7_0_start()
1054 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start()
1058 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, in uvd_v7_0_start()
1151 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, in uvd_v7_0_stop()
A Dvcn_v1_0.c846 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
853 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); in vcn_v1_0_start_spg_mode()
856 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); in vcn_v1_0_start_spg_mode()
872 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start_spg_mode()
876 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
1025 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1140 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1144 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1149 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
A Dvcn_v2_0.c861 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
990 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
997 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); in vcn_v2_0_start()
1000 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1024 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_start()
1028 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1164 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1174 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
A Duvd_v6_0.c745 WREG32(mmUVD_SOFT_RESET, in uvd_v6_0_start()
785 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_start()
795 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v6_0_start()
897 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_stop()
A Dvcn_v3_0.c1119 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_start()
1122 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_start()
1555 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1557 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1558 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1560 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_4_0_d.h83 #define mmUVD_SOFT_RESET 0x3DA0 macro
A Duvd_4_2_d.h67 #define mmUVD_SOFT_RESET 0x3da0 macro
A Duvd_3_1_d.h69 #define mmUVD_SOFT_RESET 0x3da0 macro
A Duvd_5_0_d.h73 #define mmUVD_SOFT_RESET 0x3da0 macro
A Duvd_6_0_d.h89 #define mmUVD_SOFT_RESET 0x3da0 macro
A Duvd_7_0_offset.h192 #define mmUVD_SOFT_RESET … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h378 #define mmUVD_SOFT_RESET … macro
A Dvcn_2_5_offset.h491 #define mmUVD_SOFT_RESET … macro
A Dvcn_2_0_0_offset.h672 #define mmUVD_SOFT_RESET … macro
A Dvcn_3_0_0_offset.h805 #define mmUVD_SOFT_RESET … macro

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