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Searched refs:mmUVD_STATUS (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
499 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
703 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
A Duvd_v4_2.c217 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
289 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
343 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
369 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
414 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
457 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
A Duvd_v5_0.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
387 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
413 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
475 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
A Dvcn_v1_0.c231 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
790 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
791 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
862 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
896 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
897 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1153 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1337 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1345 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
A Dvcn_v2_5.c324 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
924 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
925 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
1008 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1043 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1178 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1333 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1371 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1743 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1757 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
A Dvcn_v2_0.c266 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
939 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_0_start()
940 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start()
1014 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start()
1045 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v2_0_start()
1136 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1179 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1272 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1280 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()
1874 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in vcn_v2_0_start_sriov()
A Dvcn_v3_0.c371 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
1101 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start()
1102 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1176 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start()
1313 mmUVD_STATUS), in vcn_v3_0_start_sriov()
1518 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
1563 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v3_0_stop()
2109 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
2124 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle()
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A Duvd_v6_0.c539 if (RREG32(mmUVD_STATUS) != 0) in uvd_v6_0_hw_fini()
802 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start()
829 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
906 WREG32(mmUVD_STATUS, 0); in uvd_v6_0_stop()
1170 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) in uvd_v6_0_check_soft_reset()
A Duvd_v7_0.c817 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
907 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
929 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); in uvd_v7_0_sriov_start()
1044 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); in uvd_v7_0_start()
1074 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start()
1488 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
A Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
A Duvd_3_1_d.h78 #define mmUVD_STATUS 0x3daf macro
A Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
A Duvd_6_0_d.h98 #define mmUVD_STATUS 0x3daf macro
A Duvd_7_0_offset.h208 #define mmUVD_STATUS … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h394 #define mmUVD_STATUS … macro
A Dvcn_2_5_offset.h487 #define mmUVD_STATUS … macro
A Dvcn_2_0_0_offset.h698 #define mmUVD_STATUS … macro
A Dvcn_3_0_0_offset.h797 #define mmUVD_STATUS … macro

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