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Searched refs:mt76_set (Results 1 – 25 of 49) sorted by relevance

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/linux/drivers/net/wireless/mediatek/mt76/mt7915/
A Ddma.c91 mt76_set(dev, MT_WFDMA1_GLO_CFG, in mt7915_dma_init()
104 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, in mt7915_dma_init()
190 mt76_set(dev, MT_WFDMA0_BUSY_ENA, in mt7915_dma_init()
195 mt76_set(dev, MT_WFDMA1_BUSY_ENA, in mt7915_dma_init()
200 mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA, in mt7915_dma_init()
205 mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA, in mt7915_dma_init()
214 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7915_dma_init()
216 mt76_set(dev, MT_WFDMA1_GLO_CFG, in mt7915_dma_init()
226 mt76_set(dev, MT_WFDMA_HOST_CONFIG, in mt7915_dma_init()
252 mt76_set(dev, MT_WFDMA1_RST, in mt7915_dma_cleanup()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
A Dpci_init.c23 mt76_set(dev, MT_PBF_SYS_CTRL, val); in mt76x2_mac_pbf_init()
55 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); in mt76x2_fixup_xtal()
101 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); in mt76x2_mac_reset()
144 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); in mt76x2_power_on_rf_patch()
148 mt76_set(dev, 0x1001c, 0x30); in mt76x2_power_on_rf_patch()
153 mt76_set(dev, 0x10130, BIT(17)); in mt76x2_power_on_rf_patch()
159 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); in mt76x2_power_on_rf_patch()
168 mt76_set(dev, 0x10130, BIT(0) << shift); in mt76x2_power_on_rf()
181 mt76_set(dev, 0x530, 0xf); in mt76x2_power_on_rf()
204 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24); in mt76x2_power_on()
[all …]
A Dusb_init.c30 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); in mt76x2u_power_on_rf_patch()
34 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); in mt76x2u_power_on_rf_patch()
39 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); in mt76x2u_power_on_rf_patch()
45 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); in mt76x2u_power_on_rf_patch()
54 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); in mt76x2u_power_on_rf()
58 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); in mt76x2u_power_on_rf()
67 mt76_set(dev, 0x530, 0xf); in mt76x2u_power_on_rf()
75 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), in mt76x2u_power_on()
90 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); in mt76x2u_power_on()
97 mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0)); in mt76x2u_power_on()
A Dusb_mac.c34 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL); in mt76x2u_mac_fixup_xtal()
87 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); in mt76x2u_mac_reset()
143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
A Dmac.c37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
A Dusb_phy.c145 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); in mt76x2u_phy_set_channel()
167 mt76_set(dev, MT_BBP(TXO, 4), BIT(25)); in mt76x2u_phy_set_channel()
168 mt76_set(dev, MT_BBP(RXO, 13), BIT(8)); in mt76x2u_phy_set_channel()
A Dpci_phy.c104 mt76_set(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
105 mt76_set(dev, MT_BBP(TXBE, 5), 3); in mt76x2_phy_set_antenna()
210 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); in mt76x2_phy_set_channel()
/linux/drivers/net/wireless/mediatek/mt76/mt7921/
A Dinit.c113 mt76_set(dev, MT_TMAC_CTCR0(band), in mt7921_mac_init_band()
117 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(band), MT_WF_RMAC_MIB_RXTIME_EN); in mt7921_mac_init_band()
118 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band), MT_WF_RMAC_MIB_RXTIME_EN); in mt7921_mac_init_band()
121 mt76_set(dev, MT_MIB_SCR1(band), MT_MIB_TXDUR_EN); in mt7921_mac_init_band()
122 mt76_set(dev, MT_MIB_SCR1(band), MT_MIB_RXDUR_EN); in mt7921_mac_init_band()
135 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); in mt7921_mac_init()
137 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_RX_HDR_TRANS_EN); in mt7921_mac_init()
A Ddma.c193 mt76_set(dev, MT_WFDMA0_RST, in mt7921_dma_disable()
201 mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS); in mt7921_dma_disable()
230 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7921_dma_enable()
238 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7921_dma_enable()
241 mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT); in mt7921_dma_enable()
247 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); in mt7921_dma_enable()
279 mt76_set(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B); in mt7921_wfsys_reset()
441 mt76_set(dev, MT_WFDMA0_RST, in mt7921_dma_cleanup()
A Dpci.c338 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); in mt7921_pci_resume()
341 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7921_pci_resume()
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
A Dbeacon.c173 mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO); in mt7603_beacon_set_timer()
177 mt76_set(dev, MT_HW_INT_MASK(3), in mt7603_beacon_set_timer()
180 mt76_set(dev, MT_WF_ARB_BCN_START, in mt7603_beacon_set_timer()
187 mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); in mt7603_beacon_set_timer()
A Dmac.c63 mt76_set(dev, MT_ARB_SCR, in mt7603_mac_set_timing()
147 mt76_set(dev, addr + 0 * 4, w0); in mt7603_wtbl_init()
148 mt76_set(dev, addr + 1 * 4, w1); in mt7603_wtbl_init()
250 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_set_ps()
288 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_clear()
1343 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7603_mac_dma_start()
1362 mt76_set(dev, MT_ARB_SCR, in mt7603_mac_stop()
1383 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1); in mt7603_pse_client_reset()
1387 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2); in mt7603_pse_client_reset()
1405 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); in mt7603_dma_sched_reset()
[all …]
A Dinit.c110 mt76_set(dev, MT_SCH_4, BIT(6)); in mt7603_dma_sched_init()
180 mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT); in mt7603_mac_init()
185 mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE); in mt7603_mac_init()
191 mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS); in mt7603_mac_init()
194 mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11)); in mt7603_mac_init()
197 mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN); in mt7603_mac_init()
258 mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE); in mt7603_mac_init()
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
A Ddma.c206 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_start()
248 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
256 mt76_set(dev, 0x7158, BIT(16)); in mt7615_dma_init()
315 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); in mt7615_dma_cleanup()
A Dinit.c72 mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(0), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); in mt7615_phy_init()
73 mt76_set(dev, MT_WF_PHY_WF2_RFCTRL0(1), MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN); in mt7615_phy_init()
87 mt76_set(dev, MT_CFG_CCR, val); in mt7615_init_mac_chain()
168 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_EN); in mt7615_mac_init()
169 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_EN); in mt7615_mac_init()
177 mt76_set(dev, MT_WF_MIB_SCR0, MT_MIB_SCR0_AGG_CNT_RANGE_EN); in mt7615_mac_init()
A Dmac.c134 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); in mt7615_mac_reset_counters()
135 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); in mt7615_mac_reset_counters()
162 mt76_set(dev, MT_ARB_SCR, in mt7615_mac_set_timing()
170 mt76_set(dev, MT_ARB_SCR, in mt7615_mac_set_timing()
1671 mt76_set(dev, reg, mask); in mt7615_mac_set_scs()
1673 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); in mt7615_mac_set_scs()
1674 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); in mt7615_mac_set_scs()
1701 mt76_set(dev, rxtd, BIT(18) | BIT(29)); in mt7615_mac_enable_nf()
1702 mt76_set(dev, reg, 0x5 << 12); in mt7615_mac_enable_nf()
1718 mt76_set(dev, reg, BIT(22) | BIT(20)); in mt7615_mac_cca_stats_reset()
[all …]
A Dusb_mcu.c58 mt76_set(dev, MT_UDMA_TX_QSEL, MT_FW_DL_EN); in mt7663u_mcu_init()
A Dtestmode.c163 mt76_set(dev, MT_ARB_RQCR, rqcr_mask); in mt7615_tm_set_rx_enable()
165 mt76_set(dev, MT_ARB_SCR, in mt7615_tm_set_rx_enable()
A Dusb_sdio.c265 mt76_set(dev, MT_HIF_RST, MT_HIF_LOGIC_RST_N); in mt7663u_dma_sched_init()
267 mt76_set(dev, MT_UDMA_WLCFG_0, in mt7663u_dma_sched_init()
/linux/drivers/net/wireless/mediatek/mt76/
A Dmt76x02_phy.c41 mt76_set(dev, MT_BBP(TXBE, 5), 0x3); in mt76x02_phy_set_txdac()
155 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); in mt76x02_phy_set_band()
160 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); in mt76x02_phy_set_band()
A Dmt76x02_mmio.c29 mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff); in mt76x02_pre_tbtt_tasklet()
311 mt76_set(dev, MT_WPDMA_GLO_CFG, val); in mt76x02_dma_enable()
462 mt76_set(dev, 0x734, 0x3); in mt76x02_watchdog_reset()
480 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x02_watchdog_reset()
483 mt76_set(dev, MT_BEACON_TIME_CFG, in mt76x02_watchdog_reset()
A Dmt76x02_beacon.c87 mt76_set(dev, MT_BEACON_TIME_CFG, in mt76x02_mac_set_beacon_enable()
208 mt76_set(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_SYNC_MODE); in mt76x02_init_beacon_config()
A Dmt76x02_mac.c247 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); in mt76x02_mac_set_short_preamble()
1050 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); in mt76x02_check_mac_err()
1062 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); in mt76x02_edcca_tx_enable()
1063 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); in mt76x02_edcca_tx_enable()
1091 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x02_edcca_init()
1094 mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); in mt76x02_edcca_init()
1096 mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); in mt76x02_edcca_init()
1100 mt76_set(dev, MT_TXOP_HLDR_ET, in mt76x02_edcca_init()
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
A Dpci.c122 mt76_set(dev, MT_XO_CTRL7, 0xc03); in mt76x0e_init_hardware()
126 mt76_set(dev, MT_MAX_LEN_CFG, BIT(13)); in mt76x0e_init_hardware()
A Dphy.c370 mt76_set(dev, MT_RF_MISC, BIT(2)); in mt76x0_phy_set_chan_rf_params()
372 mt76_set(dev, MT_RF_MISC, BIT(3)); in mt76x0_phy_set_chan_rf_params()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
996 mt76_set(dev, MT_BBP(CORE, 1), 0x20); in mt76x0_phy_set_channel()

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