Searched refs:mtk_hdmi_phy_mask (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/phy/mediatek/ |
| A D | phy-mtk-hdmi-mt2701.c | 131 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC), in mtk_hdmi_pll_set_rate()
133 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR), in mtk_hdmi_pll_set_rate()
137 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL), in mtk_hdmi_pll_set_rate()
139 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV), in mtk_hdmi_pll_set_rate()
141 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN), in mtk_hdmi_pll_set_rate()
143 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP), in mtk_hdmi_pll_set_rate()
145 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC), in mtk_hdmi_pll_set_rate()
147 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR), in mtk_hdmi_pll_set_rate()
151 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS), in mtk_hdmi_pll_set_rate()
154 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP), in mtk_hdmi_pll_set_rate()
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| A D | phy-mtk-hdmi-mt8173.c | 180 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
183 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
186 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, in mtk_hdmi_pll_set_rate()
188 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
191 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, in mtk_hdmi_pll_set_rate()
193 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate()
211 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, in mtk_hdmi_pll_set_rate()
220 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, in mtk_hdmi_pll_set_rate()
223 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, in mtk_hdmi_pll_set_rate()
230 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, in mtk_hdmi_pll_set_rate()
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| A D | phy-mtk-hdmi.h | 49 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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| A D | phy-mtk-hdmi.c | 40 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, in mtk_hdmi_phy_mask() function
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