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Searched refs:num_chans (Results 1 – 25 of 54) sorted by relevance

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/linux/drivers/mailbox/
A Drockchip-mailbox.c31 int num_chans; member
84 writel_relaxed((1 << mb->mbox.num_chans) - 1, in rockchip_mbox_startup()
113 for (idx = 0; idx < mb->mbox.num_chans; idx++) { in rockchip_mbox_irq()
131 for (idx = 0; idx < mb->mbox.num_chans; idx++) { in rockchip_mbox_isr()
155 .num_chans = 4,
182 mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, in rockchip_mbox_probe()
187 mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, in rockchip_mbox_probe()
195 mb->mbox.num_chans = drv_data->num_chans; in rockchip_mbox_probe()
208 mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2); in rockchip_mbox_probe()
224 for (i = 0; i < mb->mbox.num_chans; i++) { in rockchip_mbox_probe()
A Darm_mhu_db.c66 for (i = 0; i < mbox->num_chans; i++) { in mhu_db_mbox_to_channel()
172 for (i = 0; i < mbox->num_chans; i++) in mhu_db_shutdown()
176 if (mbox->num_chans == i) { in mhu_db_shutdown()
214 for (i = 0; i < mbox->num_chans; i++) in mhu_db_mbox_xlate()
218 if (mbox->num_chans == i) { in mhu_db_mbox_xlate()
291 mhu->mbox.num_chans = max_chans; in mhu_db_probe()
A Dmailbox-sti.c104 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_to_channel()
306 for (i = 0; i < mbox->num_chans; i++) in sti_mbox_shutdown_chan()
310 if (mbox->num_chans == i) { in sti_mbox_shutdown_chan()
340 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_xlate()
457 mbox->num_chans = STI_MBOX_CHAN_MAX; in sti_mbox_probe()
A Dmailbox.c124 for (i = 0; i < mbox->num_chans; i++) { in txdone_hrtimer()
466 if (ind >= mbox->num_chans) in of_mbox_index_xlate()
483 if (!mbox || !mbox->dev || !mbox->ops || !mbox->num_chans) in mbox_controller_register()
505 for (i = 0; i < mbox->num_chans; i++) { in mbox_controller_register()
540 for (i = 0; i < mbox->num_chans; i++) in mbox_controller_unregister()
A Dtegra-hsp.c183 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { in tegra_hsp_doorbell_irq()
318 if (db->master >= chan->mbox->num_chans) { in tegra_hsp_doorbell_startup()
525 for (i = 0; i < mbox->num_chans; i++) { in tegra_hsp_db_xlate()
706 hsp->mbox_db.num_chans = 32; in tegra_hsp_probe()
710 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, in tegra_hsp_probe()
734 hsp->mbox_sm.num_chans = hsp->num_sm; in tegra_hsp_probe()
738 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, in tegra_hsp_probe()
A Dstm32-ipcc.c295 ipcc->controller.num_chans = ipcc->n_chans; in stm32_ipcc_probe()
296 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, in stm32_ipcc_probe()
304 for (i = 0; i < ipcc->controller.num_chans; i++) in stm32_ipcc_probe()
318 ipcc->controller.num_chans, ipcc->proc_id); in stm32_ipcc_probe()
A Dimx-mailbox.c452 if (chan >= mbox->num_chans) { in imx_mu_specific_xlate()
474 if (chan >= mbox->num_chans) { in imx_mu_xlate()
497 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
511 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; in imx_mu_init_specific() local
513 for (i = 0; i < num_chans; i++) { in imx_mu_init_specific()
524 priv->mbox.num_chans = num_chans; in imx_mu_init_specific()
A Darm_mhuv2.c650 while (i < mhu->mbox.num_chans) { in get_irq_chan_stat_rx()
866 mhu->mbox.num_chans = channels; in mhuv2_verify_protocol()
878 chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL); in mhuv2_allocate_channels()
924 BUG_ON(chans - mbox->chans != mbox->num_chans); in mhuv2_allocate_channels()
A Dbcm2835-mailbox.c166 mbox->controller.num_chans = 1; in bcm2835_mbox_probe()
A Darm_mhu.c137 mhu->mbox.num_chans = MHU_CHANS; in mhu_probe()
A Dplatform_mhu.c148 mhu->mbox.num_chans = MHU_CHANS; in platform_mhu_probe()
A Dqcom-apcs-ipc-mailbox.c110 apcs->mbox.num_chans = ARRAY_SIZE(apcs->mbox_chans); in qcom_apcs_ipc_probe()
A Dpcc.c697 pcc_mbox_ctrl->num_chans = count; in pcc_mbox_probe()
699 pr_info("Detected %d PCC Subspaces\n", pcc_mbox_ctrl->num_chans); in pcc_mbox_probe()
A Darmada-37xx-rwtm-mailbox.c171 mbox->controller.num_chans = 1; in armada_37xx_mbox_probe()
A Dmailbox-xgene-slimpro.c210 ctx->mb_ctrl.num_chans = i; in slimpro_mbox_probe()
A Dmailbox-mpfs.c219 mbox->controller.num_chans = 1; in mpfs_mbox_probe()
/linux/drivers/input/joystick/
A Dadc-joystick.c28 int num_chans; member
41 for (i = 0; i < joy->num_chans; ++i) { in adc_joystick_handle()
119 if (num_axes != joy->num_chans) { in adc_joystick_set_axes()
121 num_axes, joy->num_chans); in adc_joystick_set_axes()
207 joy->num_chans = i; in adc_joystick_probe()
/linux/drivers/edac/
A Dcell_edac.c175 int rc, chanmask, num_chans; in cell_edac_probe() local
200 num_chans = chanmask == 3 ? 2 : 1; in cell_edac_probe()
206 layers[1].size = num_chans; in cell_edac_probe()
/linux/drivers/firmware/
A Darm_scpi.c249 int num_chans; member
488 scpi_info->num_chans; in scpi_send_message()
859 for (i = 0; i < info->num_chans; i++) in scpi_free_channels()
939 for (; scpi_info->num_chans < count; scpi_info->num_chans++) { in scpi_probe()
941 int idx = scpi_info->num_chans; in scpi_probe()
/linux/include/linux/
A Dmailbox_controller.h78 int num_chans; member
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_socbb.h69 uint32_t num_chans; member
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c1195 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
1197 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
1227 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn303_update_bw_bounding_box()
1228 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn303_update_bw_bounding_box()
1349 if (dcn3_03_soc.num_chans <= 4) { in dcn303_update_bw_bounding_box()
1458 dc->ctx->dc_bios->vram_info.num_chans * in dcn303_resource_construct()
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
A Dp2p.c643 static s32 brcmf_p2p_escan(struct brcmf_p2p_info *p2p, u32 num_chans, in brcmf_p2p_escan() argument
659 memsize += num_chans * sizeof(__le16); in brcmf_p2p_escan()
717 if (num_chans == SOCIAL_CHAN_CNT || num_chans == (SOCIAL_CHAN_CNT + 1)) in brcmf_p2p_escan()
719 else if (num_chans == AF_PEER_SEARCH_CNT) in brcmf_p2p_escan()
727 if (num_chans == 1) { in brcmf_p2p_escan()
744 sparams->channel_num = cpu_to_le32(num_chans & in brcmf_p2p_escan()
746 for (i = 0; i < num_chans; i++) in brcmf_p2p_escan()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c201 .num_chans = 4,
262 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c1266 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
1268 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
1297 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn302_update_bw_bounding_box()
1298 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn302_update_bw_bounding_box()
1516 …_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; in dcn302_resource_construct()

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