| /linux/arch/powerpc/kernel/ |
| A D | rtas-proc.c | 513 int num_states = 0; in ppc_rtas_process_sensor() local
523 if (state < num_states) { in ppc_rtas_process_sensor()
531 if (state < num_states) { in ppc_rtas_process_sensor()
544 if (state < num_states) { in ppc_rtas_process_sensor()
552 if (state < num_states) { in ppc_rtas_process_sensor()
564 if (state < num_states) in ppc_rtas_process_sensor()
577 if (state < num_states) { in ppc_rtas_process_sensor()
584 num_states = sizeof(battery_cyclestate) / in ppc_rtas_process_sensor()
586 if (state < num_states) { in ppc_rtas_process_sensor()
595 if (state < num_states) { in ppc_rtas_process_sensor()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 211 .num_states = 5,
226 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
267 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
293 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
295 …dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states… in dcn301_update_bw_bounding_box()
296 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 148 .num_states = 1,
1215 unsigned int num_states = 0; in dcn303_update_bw_bounding_box() local
1298 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1302 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
1303 dram_speed_mts[num_states++] = in dcn303_update_bw_bounding_box()
1312 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1316 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_update_bw_bounding_box()
1318 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
1322 dcn3_03_soc.num_states = num_states; in dcn303_update_bw_bounding_box()
1323 for (i = 0; i < dcn3_03_soc.num_states; i++) { in dcn303_update_bw_bounding_box()
[all …]
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| /linux/drivers/regulator/ |
| A D | irq_helpers.c | 62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 166 .num_states = 1,
1285 unsigned int num_states = 0; in dcn302_update_bw_bounding_box() local
1371 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1375 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1383 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1384 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1385 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_update_bw_bounding_box()
1388 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_update_bw_bounding_box()
1390 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1394 dcn3_02_soc.num_states = num_states; in dcn302_update_bw_bounding_box()
[all …]
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| /linux/net/netfilter/ipvs/ |
| A D | ip_vs_proto_ah_esp.c | 119 .num_states = 1,
141 .num_states = 1,
|
| A D | ip_vs_proto_udp.c | 485 .num_states = IP_VS_UDP_S_LAST,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.c | 183 .num_states = 1,
1901 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1917 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1926 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2386 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2474 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2478 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2487 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2493 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2497 dcn3_0_soc.num_states = num_states; in dcn30_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 306 .num_states = 8
1044 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1218 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
1229 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
1316 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
1375 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn21_validate_bandwidth_fp()
1604 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { in update_bw_bounding_box()
1610 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { in update_bw_bounding_box()
1640 dcn2_1_soc.num_states = clk_table->num_entries + 1; in update_bw_bounding_box()
1644 …dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1… in update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 303 .num_states = 5,
414 .num_states = 5,
3478 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
3513 for (i = bb->num_states - 1; i > 1; i--) { in dcn20_cap_soc_clocks()
3534 bb->num_states--; in dcn20_cap_soc_clocks()
3546 if (num_states == 0) in dcn20_update_bounding_box()
3562 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
3594 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
3676 unsigned int num_states = 0; in init_soc_bounding_box() local
3902 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
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| A D | dcn20_resource.h | 103 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_socbb.h | 78 uint32_t num_states; member
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 3950 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4106 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4145 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4273 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4284 for (i = 0; i < v->soc.num_states; ++i) { in dml30_ModeSupportAndSystemConfigurationFull()
4296 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4316 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4432 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
5233 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
5294 for (i = v->soc.num_states - 1; i >= 0; i--) { in dml30_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_pp_smu.h | 229 unsigned int *clock_values_in_khz, unsigned int *num_states);
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4383 for (i = 0; i <= locals->soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4395 for (i = 0; i <= locals->soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
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| A D | display_mode_vba_20v2.c | 2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4504 for (i = 0; i <= locals->soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4516 for (i = 0; i <= locals->soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 4225 for (i = 0; i < v->soc.num_states; i++) {
4407 for (i = 0; i < v->soc.num_states; i++) {
4445 for (i = 0; i < v->soc.num_states; i++) {
4589 for (i = 0; i < v->soc.num_states; i++) {
4617 for (i = 0; i < v->soc.num_states; ++i) {
4630 for (i = 0; i < v->soc.num_states; i++) {
4650 for (i = 0; i < v->soc.num_states; i++) {
4701 for (i = 0; i < v->soc.num_states; ++i) {
4788 for (i = 0; i < v->soc.num_states; i++) {
5007 for (i = 0; i < v->soc.num_states; ++i) {
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 3672 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3714 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4068 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4092 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4099 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4176 if (i != mode_lib->vba.soc.num_states) { in dml21_ModeSupportAndSystemConfigurationFull()
4208 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4225 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4257 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4382 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 74 unsigned int num_states; member
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| A D | display_mode_lib.c | 267 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
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| /linux/include/linux/regulator/ |
| A D | driver.h | 489 int num_states; member
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_pp_smu.c | 775 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument
787 num_states)) in pp_nv_get_uclk_dpm_states()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 1359 if (loaded_bb->num_states == 1) { in set_wm_ranges()
1367 } else if (loaded_bb->num_states > 1) { in set_wm_ranges()
1368 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { in set_wm_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 220 .num_states = 5,
2039 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn31_validate_bandwidth()
2083 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
2114 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/include/ |
| A D | kgd_pp_interface.h | 395 unsigned int *num_states);
|