Searched refs:nv_entries (Results 1 – 4 of 4) sorted by relevance
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn3_build_wm_range_table()143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()149 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn3_build_wm_range_table()151 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; in dcn3_build_wm_range_table()154 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()157 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()[all …]
1883 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn31_calculate_wm_and_dlg_fp()1888 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.… in dcn31_calculate_wm_and_dlg_fp()1889 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn31_calculate_wm_and_dlg_fp()1890 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn31_calculate_wm_and_dlg_fp()1909 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn31_calculate_wm_and_dlg_fp()1910 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.… in dcn31_calculate_wm_and_dlg_fp()1911 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn31_calculate_wm_and_dlg_fp()1912 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn31_calculate_wm_and_dlg_fp()1928 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { in dcn31_calculate_wm_and_dlg_fp()1929 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.… in dcn31_calculate_wm_and_dlg_fp()[all …]
2147 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_calculate_wm_and_dlg_fp()2152 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.… in dcn30_calculate_wm_and_dlg_fp()2153 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()2154 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_calculate_wm_and_dlg_fp()2194 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_calculate_wm_and_dlg_fp()2207 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()2208 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn30_calculate_wm_and_dlg_fp()2273 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg_fp()2278 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_update_soc_for_wm_a()2279 …ml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.… in dcn30_update_soc_for_wm_a()[all …]
201 struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; member
Completed in 15 milliseconds