Searched refs:nvkm_pll_vals (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| A D | nv04.h | 6 struct nvkm_pll_vals;
20 void setPLL_single(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
21 void setPLL_double_highregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
22 void setPLL_double_lowregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
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| A D | nv04.c | 144 struct nvkm_pll_vals *pv) in setPLL_single()
199 struct nvkm_pll_vals *pv) in setPLL_double_highregs()
277 struct nvkm_pll_vals *pv) in setPLL_double_lowregs()
360 struct nvkm_pll_vals pv; in nv04_devinit_pll_set()
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| A D | clk.h | 8 struct nvkm_pll_vals;
118 struct nvkm_pll_vals *pv);
119 int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| A D | priv.h | 25 struct nvkm_pll_vals *);
26 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
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| A D | nv04.c | 33 int clk, struct nvkm_pll_vals *pv) in nv04_clk_pll_calc()
49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog()
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| A D | pll.h | 5 struct nvkm_pll_vals { struct
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| /linux/drivers/gpu/drm/nouveau/dispnv04/ |
| A D | hw.c | 133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll()
165 struct nvkm_pll_vals *pllvals) in nouveau_hw_get_pllvals()
205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) in nouveau_hw_pllvals_to_clk()
218 struct nvkm_pll_vals pllvals; in nouveau_hw_get_clock()
265 struct nvkm_pll_vals pv; in nouveau_hw_fix_bad_vpll()
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| A D | hw.h | 44 struct nvkm_pll_vals *pllvals);
45 int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);
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| A D | disp.h | 42 struct nvkm_pll_vals pllvals;
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| A D | crtc.c | 126 struct nvkm_pll_vals *pv = ®p->pllvals; in nv_crtc_calc_state_ext()
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