Searched refs:od_enabled (Results 1 – 16 of 16) sorted by relevance
106 hwmgr->od_enabled = false; in hwmgr_early_init()111 hwmgr->od_enabled = false; in hwmgr_early_init()126 hwmgr->od_enabled = false; in hwmgr_early_init()181 hwmgr->od_enabled = false; in hwmgr_early_init()463 hwmgr->od_enabled = true; in hwmgr_set_user_specify_caps()
581 hwmgr->od_enabled = 1; in smu10_hwmgr_backend_init()1060 if (hwmgr->od_enabled) { in smu10_print_clock_levels()1076 if (hwmgr->od_enabled) { in smu10_print_clock_levels()1533 if (!hwmgr->od_enabled) { in smu10_set_fine_grain_clk_vol()
1619 if (hwmgr->od_enabled) in vega10_populate_single_gfx_level()1684 if (hwmgr->od_enabled) { in vega10_populate_single_soc_level()1787 if (hwmgr->od_enabled) in vega10_populate_vddc_soc_levels()1823 if (hwmgr->od_enabled) in vega10_populate_single_memory_level()2569 if (hwmgr->od_enabled) { in vega10_init_smc_table()3446 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()3452 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()4721 if (hwmgr->od_enabled) { in vega10_print_clock_levels()4731 if (hwmgr->od_enabled) { in vega10_print_clock_levels()4741 if (hwmgr->od_enabled) { in vega10_print_clock_levels()[all …]
1078 if (hwmgr->od_enabled) { in smu7_setup_default_dpm_tables()4202 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()4209 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()4246 if ((!hwmgr->od_enabled || force_trim) in smu7_trim_single_dpm_states()4965 if (hwmgr->od_enabled) { in smu7_print_clock_levels()4974 if (hwmgr->od_enabled) { in smu7_print_clock_levels()4983 if (hwmgr->od_enabled) { in smu7_print_clock_levels()5444 if (!hwmgr->od_enabled) { in smu7_odn_edit_dpm_table()
1125 hwmgr->od_enabled = false; in vega20_od8_set_feature_capabilities()
1356 if (!smu->od_enabled || !od_table || !od_settings) in navi10_print_clk_levels()1365 if (!smu->od_enabled || !od_table || !od_settings) in navi10_print_clk_levels()1373 if (!smu->od_enabled || !od_table || !od_settings) in navi10_print_clk_levels()1398 if (!smu->od_enabled || !od_table || !od_settings) in navi10_print_clk_levels()2174 if (smu->od_enabled && in navi10_get_power_limit()2385 if (!smu->od_enabled) { in navi10_od_edit_dpm_table()
1096 if (!smu->od_enabled || !od_table || !od_settings) in sienna_cichlid_print_clk_levels()1107 if (!smu->od_enabled || !od_table || !od_settings) in sienna_cichlid_print_clk_levels()1118 if (!smu->od_enabled || !od_table || !od_settings) in sienna_cichlid_print_clk_levels()1135 if (!smu->od_enabled || !od_table || !od_settings) in sienna_cichlid_print_clk_levels()1807 if (smu->od_enabled) { in sienna_cichlid_get_power_limit()1965 if (!smu->od_enabled) { in sienna_cichlid_od_edit_dpm_table()
1373 if (smu->od_enabled) { in arcturus_get_power_limit()
580 smu->od_enabled = true; in smu_set_funcs()612 smu->od_enabled =false; in smu_set_funcs()617 smu->od_enabled = true; in smu_set_funcs()707 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { in smu_late_init()
1018 if (hwmgr->od_enabled) { in pp_set_power_limit()1057 if (hwmgr->od_enabled) { in pp_get_power_limit()
507 bool od_enabled; member
807 bool od_enabled; member
949 if (hwmgr->od_enabled) in fiji_populate_single_graphic_level()1171 if (hwmgr->od_enabled) in fiji_populate_single_memory_level()
969 if (hwmgr->od_enabled) in polaris10_populate_single_graphic_level()1164 if (hwmgr->od_enabled) in polaris10_populate_single_memory_level()
629 if (hwmgr->od_enabled) in tonga_populate_single_graphic_level()977 if (hwmgr->od_enabled) in tonga_populate_single_memory_level()
2069 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) || in default_attr_update()2071 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) in default_attr_update()
Completed in 83 milliseconds