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Searched refs:op2 (Results 1 – 25 of 43) sorted by relevance

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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
A Dphy_qmath.c13 u16 qm_mulu16(u16 op1, u16 op2) in qm_mulu16() argument
15 return (u16) (((u32) op1 * (u32) op2) >> 16); in qm_mulu16()
26 s16 qm_muls16(s16 op1, s16 op2) in qm_muls16() argument
32 result = ((s32) (op1) * (s32) (op2)); in qm_muls16()
42 s32 qm_add32(s32 op1, s32 op2) in qm_add32() argument
45 result = op1 + op2; in qm_add32()
46 if (op1 < 0 && op2 < 0 && result > 0) in qm_add32()
59 s16 qm_add16(s16 op1, s16 op2) in qm_add16() argument
62 s32 temp = (s32) op1 + (s32) op2; in qm_add16()
78 s16 qm_sub16(s16 op1, s16 op2) in qm_sub16() argument
[all …]
A Dphy_qmath.h11 u16 qm_mulu16(u16 op1, u16 op2);
13 s16 qm_muls16(s16 op1, s16 op2);
15 s32 qm_add32(s32 op1, s32 op2);
17 s16 qm_add16(s16 op1, s16 op2);
19 s16 qm_sub16(s16 op1, s16 op2);
/linux/arch/arc/include/asm/
A Datomic64-arcv2.h49 #define ATOMIC64_OP(op, op1, op2) \ argument
58 " " #op2 " %H0, %H0, %H2 \n" \
75 " " #op2 " %H0, %H0, %H2 \n" \
97 " " #op2 " %H1, %H0, %H3 \n" \
115 #define ATOMIC64_OPS(op, op1, op2) \ argument
116 ATOMIC64_OP(op, op1, op2) \
117 ATOMIC64_OP_RETURN(op, op1, op2) \
118 ATOMIC64_FETCH_OP(op, op1, op2)
124 #define ATOMIC64_OPS(op, op1, op2) \ argument
125 ATOMIC64_OP(op, op1, op2) \
[all …]
/linux/include/trace/events/
A Dhost1x.h50 TP_PROTO(const char *name, u32 op1, u32 op2),
52 TP_ARGS(name, op1, op2),
57 __field(u32, op2)
63 __entry->op2 = op2;
67 __entry->name, __entry->op1, __entry->op2)
71 TP_PROTO(const char *name, u32 op1, u32 op2, u32 op3, u32 op4),
73 TP_ARGS(name, op1, op2, op3, op4),
78 __field(u32, op2)
86 __entry->op2 = op2;
92 __entry->name, __entry->op1, __entry->op2, __entry->op3,
/linux/tools/objtool/arch/x86/
A Ddecode.c115 unsigned char op1, op2, in arch_decode_instruction() local
141 op2 = insn.opcode.bytes[1]; in arch_decode_instruction()
467 if (op2 == 0x01) { in arch_decode_instruction()
474 } else if (op2 >= 0x80 && op2 <= 0x8f) { in arch_decode_instruction()
478 } else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 || in arch_decode_instruction()
479 op2 == 0x35) { in arch_decode_instruction()
484 } else if (op2 == 0x0b || op2 == 0xb9) { in arch_decode_instruction()
489 } else if (op2 == 0x0d || op2 == 0x1f) { in arch_decode_instruction()
494 } else if (op2 == 0xa0 || op2 == 0xa8) { in arch_decode_instruction()
502 } else if (op2 == 0xa1 || op2 == 0xa9) { in arch_decode_instruction()
/linux/drivers/gpu/drm/i915/gt/
A Dintel_gpu_commands.h258 #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) argument
261 #define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) argument
262 #define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) argument
270 #define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) argument
271 #define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) argument
/linux/arch/arm/include/asm/
A Datomic.h304 #define ATOMIC64_OP(op, op1, op2) \ argument
314 " " #op2 " %R0, %R0, %R4\n" \
335 " " #op2 " %R0, %R0, %R4\n" \
358 " " #op2 " %R1, %R0, %R5\n" \
369 #define ATOMIC64_OPS(op, op1, op2) \ argument
370 ATOMIC64_OP(op, op1, op2) \
371 ATOMIC64_OP_RETURN(op, op1, op2) \
372 ATOMIC64_FETCH_OP(op, op1, op2)
383 #define ATOMIC64_OPS(op, op1, op2) \ in ATOMIC64_OPS() argument
384 ATOMIC64_OP(op, op1, op2) \ in ATOMIC64_OPS()
[all …]
/linux/lib/zlib_dfltcc/
A Ddfltcc_util.h31 const Byte **op2, in dfltcc() argument
38 const Byte *t4 = op2 ? *op2 : NULL; in dfltcc()
66 if (op2) in dfltcc()
67 *op2 = t4; in dfltcc()
/linux/arch/sh/kernel/
A Dkprobes.c149 struct kprobe *op1, *op2; in prepare_singlestep() local
154 op2 = this_cpu_ptr(&saved_next_opcode2); in prepare_singlestep()
178 op2->addr = in prepare_singlestep()
180 op2->opcode = *(op2->addr); in prepare_singlestep()
181 arch_arm_kprobe(op2); in prepare_singlestep()
188 op2->addr = in prepare_singlestep()
190 op2->opcode = *(op2->addr); in prepare_singlestep()
191 arch_arm_kprobe(op2); in prepare_singlestep()
/linux/arch/sparc/kernel/
A Duprobes.c60 u32 op2 = (insn >> 22) & 0x7; in arch_uprobe_copy_ixol() local
63 (op2 == 1 || op2 == 2 || op2 == 3 || op2 == 5 || op2 == 6) && in arch_uprobe_copy_ixol()
/linux/arch/x86/crypto/
A Dcast6-avx-x86_64-asm_64.S85 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument
94 op2 s3(, RID1, 4), dst ## d; \
111 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument
112 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
113 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
115 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
118 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
130 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
A Dcast5-avx-x86_64-asm_64.S85 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument
94 op2 s3(, RID1, 4), dst ## d; \
111 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument
112 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
113 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
115 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
118 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
130 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
/linux/arch/powerpc/math-emu/
A Dmath.c28 #define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \
228 void *op0 = NULL, *op1 = NULL, *op2 = NULL, *op3 = NULL; in do_mathemu() local
334 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu()
340 op2 = (void *)&current->thread.TS_FPR((insn >> 6) & 0x1f); in do_mathemu()
346 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu()
400 op2 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu()
407 op2 = (void *)((insn >> 18) & 0x7); in do_mathemu()
435 eflag = func(op0, op1, op2, op3); in do_mathemu()
/linux/drivers/gpu/host1x/
A Dcdma.c138 static void host1x_pushbuffer_push(struct push_buffer *pb, u32 op1, u32 op2) in host1x_pushbuffer_push() argument
144 *(p++) = op2; in host1x_pushbuffer_push()
567 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2) in host1x_cdma_push() argument
575 op1, op2); in host1x_cdma_push()
585 host1x_pushbuffer_push(pb, op1, op2); in host1x_cdma_push()
597 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2, in host1x_cdma_push_wide() argument
607 trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2, in host1x_cdma_push_wide()
637 host1x_pushbuffer_push(pb, op1, op2); in host1x_cdma_push_wide()
A Dcdma.h81 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);
82 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,
/linux/lib/zstd/decompress/
A Dhuf_decompress.c383 BYTE* op2 = opStart2; in HUF_decompress4X1_usingDTable_internal_body() local
399 HUF_DECODE_SYMBOLX1_2(op2, &bitD2); in HUF_decompress4X1_usingDTable_internal_body()
403 HUF_DECODE_SYMBOLX1_1(op2, &bitD2); in HUF_decompress4X1_usingDTable_internal_body()
407 HUF_DECODE_SYMBOLX1_2(op2, &bitD2); in HUF_decompress4X1_usingDTable_internal_body()
411 HUF_DECODE_SYMBOLX1_0(op2, &bitD2); in HUF_decompress4X1_usingDTable_internal_body()
836 BYTE* op2 = opStart2; in HUF_decompress4X2_usingDTable_internal_body() local
856 HUF_DECODE_SYMBOLX2_2(op2, &bitD2); in HUF_decompress4X2_usingDTable_internal_body()
857 HUF_DECODE_SYMBOLX2_1(op2, &bitD2); in HUF_decompress4X2_usingDTable_internal_body()
858 HUF_DECODE_SYMBOLX2_2(op2, &bitD2); in HUF_decompress4X2_usingDTable_internal_body()
859 HUF_DECODE_SYMBOLX2_0(op2, &bitD2); in HUF_decompress4X2_usingDTable_internal_body()
[all …]
/linux/arch/arm64/include/asm/
A Desr.h180 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument
183 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
292 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ argument
294 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
A Dsysreg.h39 #define sys_reg(op0, op1, crn, crm, op2) \ argument
42 ((op2) << Op2_shift))
91 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) argument
108 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ argument
109 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
475 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/linux/drivers/gpu/host1x/hw/
A Dchannel_hw.c105 u32 op2, op3; in submit_gathers() local
107 op2 = lower_32_bits(addr); in submit_gathers()
117 host1x_cdma_push_wide(cdma, op1, op2, op3, op4); in submit_gathers()
126 host1x_cdma_push(cdma, op1, op2); in submit_gathers()
/linux/arch/x86/kvm/svm/
A Dsvm_ops.h29 #define svm_asm2(insn, op1, op2, clobber...) \ argument
33 :: op1, op2 : clobber : fault); \
/linux/arch/s390/net/
A Dbpf_jit_comp.c199 #define _EMIT6(op1, op2) \ argument
203 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
208 #define _EMIT6_DISP(op1, op2, disp) \ argument
211 _EMIT6((op1) | __disp, op2); \
214 #define _EMIT6_DISP_LH(op1, op2, disp) \ argument
219 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
222 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ argument
225 reg_high(b3) << 8, op2, disp); \
235 (op2) | (mask) << 12); \
244 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
[all …]
/linux/tools/arch/arm64/include/asm/
A Dsysreg.h36 #define sys_reg(op0, op1, crn, crm, op2) \ argument
39 ((op2) << Op2_shift))
88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) argument
105 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ argument
106 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
472 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/linux/tools/arch/arm/include/uapi/asm/
A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
171 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
/linux/tools/arch/arm64/include/uapi/asm/
A Dkvm.h231 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
237 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
/linux/arch/arm64/include/uapi/asm/
A Dkvm.h231 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
237 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))

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