| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_mpc.c | 138 unsigned int opp_id; in mpc1_is_mpcc_idle() local
363 int opp_id; in mpc1_mpc_init() local
375 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { in mpc1_mpc_init()
376 if (REG(MUX[opp_id])) in mpc1_mpc_init()
384 int opp_id; in mpc1_mpc_init_single_inst() local
395 if (opp_id < MAX_OPP && REG(MUX[opp_id])) in mpc1_mpc_init_single_inst()
405 unsigned int opp_id; in mpc1_init_mpcc_list_from_hw() local
424 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { in mpc1_init_mpcc_list_from_hw()
435 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { in mpc1_init_mpcc_list_from_hw()
476 if (opp_id < MAX_OPP && REG(MUX[opp_id])) in mpc1_get_mpc_out_mux()
[all …]
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| A D | dcn10_mpc.h | 201 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
203 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
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| A D | dcn10_hw_sequencer.h | 68 int opp_id);
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| A D | dcn10_hw_sequencer_debug.c | 399 if (s.opp_id != 0xf) { in dcn10_get_mpcc_states()
401 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_get_mpcc_states()
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| A D | dcn10_hw_sequencer.c | 339 if (s.opp_id != 0xf) in dcn10_log_hw_state()
341 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, in dcn10_log_hw_state()
1215 int opp_id = hubp->opp_id; in dcn10_plane_atomic_disable() local
1223 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) in dcn10_plane_atomic_disable()
1345 hubp->opp_id = OPP_ID_INVALID; in dcn10_init_pipes()
1348 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
2455 int opp_id) in dcn10_program_output_csc() argument
2589 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn10_update_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_optc.c | 43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
61 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc31_set_odm_combine()
63 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc31_set_odm_combine()
76 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine()
77 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc31_set_odm_combine()
81 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine()
82 OPTC_SEG1_SRC_SEL, opp_id[1], in optc31_set_odm_combine()
83 OPTC_SEG2_SRC_SEL, opp_id[2], in optc31_set_odm_combine()
84 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc31_set_odm_combine()
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| A D | dcn31_hubp.c | 99 hubp2->base.opp_id = OPP_ID_INVALID; in hubp31_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_optc.c | 210 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
235 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc3_set_odm_combine()
240 …memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (o… in optc3_set_odm_combine()
250 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
251 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc3_set_odm_combine()
255 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
256 OPTC_SEG1_SRC_SEL, opp_id[1], in optc3_set_odm_combine()
257 OPTC_SEG2_SRC_SEL, opp_id[2], in optc3_set_odm_combine()
258 OPTC_SEG3_SRC_SEL, opp_id[3]); in optc3_set_odm_combine()
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| A D | dcn30_mpc.c | 85 int opp_id, in mpc3_set_out_rate_control() argument
92 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
97 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
380 int opp_id, in mpc3_set_denorm() argument
413 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc3_set_denorm()
419 int opp_id, in mpc3_set_denorm_clamp() argument
425 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc3_set_denorm_clamp()
428 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc3_set_denorm_clamp()
431 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc3_set_denorm_clamp()
1236 int opp_id, in mpc3_set_output_csc() argument
[all …]
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| A D | dcn30_mpc.h | 810 int opp_id,
815 int opp_id,
820 int opp_id,
826 int opp_id,
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| A D | dcn30_hubp.c | 525 hubp2->base.opp_id = OPP_ID_INVALID; in hubp3_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | mpc.h | 127 int opp_id; /* The OPP instance that owns this MPC tree */ member
141 uint32_t opp_id; member
239 int opp_id,
298 int opp_id,
303 int opp_id,
307 int opp_id,
312 int opp_id,
339 int opp_id,
365 int opp_id);
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| A D | hubp.h | 63 int opp_id; member
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| A D | timing_generator.h | 294 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_mpc.c | 75 int opp_id, in mpc2_set_denorm() argument
107 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm()
113 int opp_id, in mpc2_set_denorm_clamp() argument
118 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
133 int opp_id, in mpc2_set_output_csc() argument
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
173 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_output_csc()
[all …]
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| A D | dcn20_optc.c | 219 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
242 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc2_set_odm_combine()
250 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine()
251 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
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| A D | dcn20_mpc.h | 284 int opp_id,
289 int opp_id,
294 int opp_id,
300 int opp_id,
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| A D | dcn20_hwseq.h | 51 int opp_id);
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| A D | dcn20_optc.h | 104 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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| A D | dcn20_hwseq.c | 772 int opp_id) in dcn20_program_output_csc() argument
784 opp_id, in dcn20_program_output_csc()
790 opp_id, in dcn20_program_output_csc()
1529 hubp->opp_id); in dcn20_update_dchubp_dpp()
2370 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn20_update_mpcc()
2534 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
2553 hubp->opp_id = OPP_ID_INVALID; in dcn20_fpga_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_mpc.c | 44 int opp_id, in mpc201_set_out_rate_control() argument
51 REG_UPDATE_2(MUX[opp_id], in mpc201_set_out_rate_control()
56 REG_UPDATE_3(MUX[opp_id], in mpc201_set_out_rate_control()
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| A D | dcn201_hubp.c | 146 hubp201->base.opp_id = OPP_ID_INVALID; in dcn201_hubp_construct()
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| A D | dcn201_hwseq.c | 308 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
327 hubp->opp_id = OPP_ID_INVALID; in dcn201_init_hw()
534 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | hw_sequencer.h | 163 uint16_t *matrix, int opp_id);
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| /linux/Documentation/arm/omap/ |
| A D | omap_pm.rst | 127 7. `(*pdata->dsp_set_min_opp)(u8 opp_id)`
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