Searched refs:output_mask (Results 1 – 13 of 13) sorted by relevance
618 u16 output_mask = channel->output_mask; in idtcm_sync_pps_output() local644 qn = output_mask & 0x1; in idtcm_sync_pps_output()645 output_mask = output_mask >> 1; in idtcm_sync_pps_output()647 output_mask = output_mask >> 1; in idtcm_sync_pps_output()651 output_mask = output_mask >> 1; in idtcm_sync_pps_output()656 output_mask = output_mask >> 1; in idtcm_sync_pps_output()658 qn = output_mask & 0x1; in idtcm_sync_pps_output()659 output_mask = output_mask >> 1; in idtcm_sync_pps_output()662 output_mask = output_mask >> 1; in idtcm_sync_pps_output()665 output_mask = output_mask >> 1; in idtcm_sync_pps_output()[all …]
510 idt82p33->channel[0].output_mask = val; in idt82p33_check_and_set_masks()513 idt82p33->channel[1].output_mask = val; in idt82p33_check_and_set_masks()532 i, idt82p33->channel[i].output_mask); in idt82p33_display_masks()601 mask = channel->output_mask; in idt82p33_output_mask_enable()1021 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; in idt82p33_probe()1022 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; in idt82p33_probe()
108 u16 output_mask; member
129 u8 output_mask; member
25 u8 output_mask; member
233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()511 chip->variant.output_mask |= BIT(val); in pwm_samsung_parse_dt()570 if (chip->variant.output_mask & BIT(chan)) in pwm_samsung_probe()619 if (our_chip->variant.output_mask & BIT(i)) in pwm_samsung_resume()
129 u64 output_mask; member
626 if (pt->output_mask != reg) { in pt_config_buffer()627 pt->output_mask = reg; in pt_config_buffer()947 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask); in pt_read_offset()949 buf->output_off = pt->output_mask >> 32; in pt_read_offset()952 buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7; in pt_read_offset()
178 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in s3c64xx_set_timer_source()179 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); in s3c64xx_set_timer_source()
227 s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in s3c24xx_set_timer_source()228 s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); in s3c24xx_set_timer_source()
380 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); in _samsung_pwm_clocksource_init()435 pwm.variant.output_mask |= 1 << val; in samsung_pwm_alloc()
57 u64 output_mask; member
1017 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); in pt_load_msr()1031 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); in pt_save_msr()1882 msr_info->data = vmx->pt_desc.guest.output_mask; in vmx_get_msr()2196 vmx->pt_desc.guest.output_mask = data; in vmx_set_msr()4366 vmx->pt_desc.guest.output_mask = 0x7F; in init_vmcs()
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