Searched refs:pcie_reg_base (Results 1 – 3 of 3) sorted by relevance
83 void __iomem *pcie_reg_base; member123 writel(0x0, PCIE_HDP_INT_EN(ps->pcie_reg_base)); in qtnf_disable_hdp_irqs()317 PCIE_HDP_HHBM_BUF_PTR_H(ps->pcie_reg_base)); in pearl_skb2rbd_attach()320 PCIE_HDP_HHBM_BUF_PTR(ps->pcie_reg_base)); in pearl_skb2rbd_attach()386 val = readl(PCIE_HHBM_CONFIG(ps->pcie_reg_base)); in pearl_hhbm_init()388 writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base)); in pearl_hhbm_init()394 writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base)); in pearl_hhbm_init()588 PCIE_HDP_HOST_WR_DESC0(ps->pcie_reg_base)); in qtnf_pcie_skb_send()888 readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base)) in qtnf_dbg_hdp_stats()897 readl(PCIE_HDP_TX0DMA_CNT(ps->pcie_reg_base)) in qtnf_dbg_hdp_stats()[all …]
190 pcie->pcie_reg_base = res->start; in mobiveil_pcie_parse_dt()204 phys_addr_t msg_addr = pcie->pcie_reg_base; in mobiveil_pcie_enable_msi()374 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); in mobiveil_compose_msi_msg()
170 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */ member
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