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Searched refs:pfit_control (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_panel.c332 u32 *pfit_control) in i965_scale_aspect() argument
343 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
346 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
380 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
396 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
402 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
447 pfit_control |= PFIT_ENABLE; in gmch_panel_fitting()
449 pfit_control |= PFIT_SCALING_AUTO; in gmch_panel_fitting()
451 pfit_control |= (VERT_AUTO_SCALE | in gmch_panel_fitting()
468 if ((pfit_control & PFIT_ENABLE) == 0) { in gmch_panel_fitting()
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A Dintel_overlay.c936 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); in update_pfit_vscale_ratio() local
946 if (pfit_control & VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
/linux/drivers/gpu/drm/gma500/
A Dcdv_intel_lvds.c265 u32 pfit_control; in cdv_intel_lvds_mode_set() local
280 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in cdv_intel_lvds_mode_set()
284 pfit_control = 0; in cdv_intel_lvds_mode_set()
286 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_lvds_mode_set()
289 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in cdv_intel_lvds_mode_set()
291 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
A Dpsb_intel_lvds.c460 u32 pfit_control; in psb_intel_lvds_mode_set() local
475 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in psb_intel_lvds_mode_set()
479 pfit_control = 0; in psb_intel_lvds_mode_set()
482 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in psb_intel_lvds_mode_set()
484 REG_WRITE(PFIT_CONTROL, pfit_control); in psb_intel_lvds_mode_set()
A Doaktrail_crtc.c346 u32 pfit_control; in oaktrail_panel_fitter_pipe() local
348 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
351 if ((pfit_control & PFIT_ENABLE) == 0) in oaktrail_panel_fitter_pipe()
353 return (pfit_control >> 29) & 3; in oaktrail_panel_fitter_pipe()
A Dpsb_intel_display.c80 u32 pfit_control; in psb_intel_panel_fitter_pipe() local
82 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
85 if ((pfit_control & PFIT_ENABLE) == 0) in psb_intel_panel_fitter_pipe()
A Dcdv_intel_display.c560 u32 pfit_control; in cdv_intel_panel_fitter_pipe() local
562 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
565 if ((pfit_control & PFIT_ENABLE) == 0) in cdv_intel_panel_fitter_pipe()
567 return (pfit_control >> 29) & 0x3; in cdv_intel_panel_fitter_pipe()
A Dcdv_intel_dp.c1093 uint32_t pfit_control; in cdv_intel_dp_mode_set() local
1098 pfit_control = PFIT_ENABLE; in cdv_intel_dp_mode_set()
1100 pfit_control = 0; in cdv_intel_dp_mode_set()
1102 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_dp_mode_set()
1104 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_dp_mode_set()

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