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Searched refs:phase (Results 1 – 25 of 418) sorted by relevance

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/linux/drivers/clk/hisilicon/
A Dclk-hisi-phase.c47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
78 val = readl(phase->reg); in hisi_clk_set_phase()
79 val &= ~phase->mask; in hisi_clk_set_phase()
80 val |= regval << phase->shift; in hisi_clk_set_phase()
81 writel(val, phase->reg); in hisi_clk_set_phase()
97 struct clk_hisi_phase *phase; in clk_register_hisi_phase() local
101 if (!phase) in clk_register_hisi_phase()
111 phase->shift = clks->shift; in clk_register_hisi_phase()
113 phase->lock = lock; in clk_register_hisi_phase()
[all …]
/linux/drivers/clk/sunxi-ng/
A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
/linux/drivers/clk/sunxi/
A Dclk-mod0.c179 value = readl(phase->reg); in mmc_get_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
324 struct mmc_phase *phase; in sunxi_mmc_setup() local
326 phase = kmalloc(sizeof(*phase), GFP_KERNEL); in sunxi_mmc_setup()
327 if (!phase) in sunxi_mmc_setup()
330 phase->hw.init = &init; in sunxi_mmc_setup()
331 phase->reg = reg; in sunxi_mmc_setup()
332 phase->lock = lock; in sunxi_mmc_setup()
335 phase->offset = 8; in sunxi_mmc_setup()
337 phase->offset = 20; in sunxi_mmc_setup()
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/linux/drivers/gpu/drm/tidss/
A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/linux/drivers/hwmon/pmbus/
A Dmp2888.c98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
133 switch (phase) { in mp2888_read_phases()
163 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
175 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
185 if (phase != 0xff) in mp2888_read_word_data()
186 return mp2888_read_phases(client, data, page, phase); in mp2888_read_word_data()
188 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
199 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
212 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
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A Dmp2975.c122 int page, int phase, u8 reg) in mp2975_read_phase() argument
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
163 int page, int phase) in mp2975_read_phases() argument
168 switch (phase) { in mp2975_read_phases()
170 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
174 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
185 switch (phase) { in mp2975_read_phases()
218 int phase, int reg) in mp2975_read_word_data() argument
244 ret = mp2975_read_word_helper(client, page, phase, in mp2975_read_word_data()
254 ret = mp2975_read_word_helper(client, page, phase, in mp2975_read_word_data()
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A Dir35221.c25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
A Dltc3815.c73 int phase, int reg) in ltc3815_read_word_data() argument
79 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
83 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
87 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
91 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
95 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
/linux/lib/zstd/compress/
A Dzstd_cwksp.h149 ZSTD_cwksp_alloc_phase_e phase; member
196 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
197 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
198 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
202 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
216 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
234 ZSTD_cwksp_internal_advance_phase(ws, phase); in ZSTD_cwksp_reserve_internal()
288 ZSTD_cwksp_internal_advance_phase(ws, phase); in ZSTD_cwksp_reserve_table()
388 if (ws->phase > ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_clear()
389 ws->phase = ZSTD_cwksp_alloc_buffers; in ZSTD_cwksp_clear()
[all …]
/linux/drivers/char/
A Dppdev.c397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
458 pp->state.phase = phase; in pp_do_ioctl()
461 pp->pdev->port->ieee1284.phase = phase; in pp_do_ioctl()
472 phase = pp->state.phase; in pp_do_ioctl()
544 pp->state.phase = info->phase; in pp_do_ioctl()
546 info->phase = pp->saved_state.phase; in pp_do_ioctl()
722 pp->saved_state.phase = info->phase; in pp_release()
724 info->phase = pp->state.phase; in pp_release()
741 pp->state.phase = info->phase; in pp_release()
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/linux/drivers/gpu/drm/imx/dcss/
A Ddcss-scaler.c178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
237 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
239 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
243 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
589 int i, phase; in dcss_scaler_program_5_coef_set() local
624 int i, phase; in dcss_scaler_program_7_coef_set() local
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/linux/drivers/parport/
A Dieee1284_ops.c171 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
345 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in ecp_forward_to_reverse()
374 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in ecp_reverse_to_forward()
401 if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE) in parport_ieee1284_ecp_write_data()
405 port->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_ecp_write_data()
467 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_ecp_write_data()
489 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) in parport_ieee1284_ecp_read_data()
493 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_ecp_read_data()
612 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_ecp_read_data()
635 port->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_ecp_write_addr()
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/linux/drivers/net/wwan/iosm/
A Diosm_ipc_imem_ops.c66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
134 enum ipc_phase phase; in ipc_imem_is_channel_active() local
137 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
140 switch (phase) { in ipc_imem_is_channel_active()
162 channel->channel_id, phase); in ipc_imem_is_channel_active()
188 curr_phase = ipc_imem->phase; in ipc_imem_sys_cdev_close()
308 ipc_imem->phase == IPC_P_OFF_REQ) in ipc_imem_sys_cdev_write()
334 enum ipc_phase phase; in ipc_imem_sys_devlink_open() local
338 switch (phase) { in ipc_imem_sys_devlink_open()
514 ipc_imem->phase = IPC_P_PSI; in ipc_imem_sys_psi_transfer()
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A Diosm_ipc_imem.c582 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
594 switch (phase) { in ipc_imem_handle_irq()
697 if ((phase == IPC_P_PSI || phase == IPC_P_EBL) && in ipc_imem_handle_irq()
784 return ipc_imem->phase; in ipc_imem_phase_update_check()
840 ipc_imem->phase : in ipc_imem_phase_update()
846 switch (phase) { in ipc_imem_phase_get_string()
1189 ipc_imem->phase = IPC_P_OFF; in ipc_imem_cleanup()
1199 enum ipc_phase phase; in ipc_imem_config() local
1213 switch (phase) { in ipc_imem_config()
1244 phase); in ipc_imem_config()
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/linux/include/trace/events/
A Dclk.h200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
/linux/drivers/char/ipmi/
A Dkcs_bmc_cdev_ipmi.c76 enum kcs_ipmi_phases phase; member
133 priv->phase = KCS_PHASE_ERROR; in kcs_bmc_ipmi_force_abort()
145 switch (priv->phase) { in kcs_bmc_ipmi_handle_data()
147 priv->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_ipmi_handle_data()
165 priv->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_ipmi_handle_data()
187 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
198 priv->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_ipmi_handle_data()
205 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
224 priv->phase = KCS_PHASE_WRITE_START; in kcs_bmc_ipmi_handle_cmd()
368 priv->phase = KCS_PHASE_WAIT_READ; in kcs_bmc_ipmi_read()
[all …]
/linux/drivers/mmc/core/
A Dhost.c224 struct mmc_clk_phase *phase) in mmc_of_parse_timing_phase() argument
230 phase->valid = !rc; in mmc_of_parse_timing_phase()
231 if (phase->valid) { in mmc_of_parse_timing_phase()
232 phase->in_deg = degrees[0]; in mmc_of_parse_timing_phase()
233 phase->out_deg = degrees[1]; in mmc_of_parse_timing_phase()
243 &map->phase[MMC_TIMING_LEGACY]); in mmc_of_parse_clk_phase()
245 &map->phase[MMC_TIMING_MMC_HS]); in mmc_of_parse_clk_phase()
247 &map->phase[MMC_TIMING_SD_HS]); in mmc_of_parse_clk_phase()
249 &map->phase[MMC_TIMING_UHS_SDR12]); in mmc_of_parse_clk_phase()
251 &map->phase[MMC_TIMING_UHS_SDR25]); in mmc_of_parse_clk_phase()
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/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
85 phase = 10; in dccg21_update_dpp_dto()
89 DPPCLK0_DTO_PHASE, phase, in dccg21_update_dpp_dto()
/linux/drivers/scsi/pcmcia/
A Dnsp_cs.c366 unsigned char phase, arbit; in nsphw_start_selection() local
371 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
378 SCpnt->SCp.phase = PH_ARBSTART; in nsphw_start_selection()
545 unsigned char phase, i_src; in nsp_expect_signal() local
552 if (phase == 0xff) { in nsp_expect_signal()
561 if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) { in nsp_expect_signal()
598 if (phase & BUSMON_IO) { in nsp_xfer()
636 SCpnt->SCp.phase = PH_DATA; in nsp_dataphase_bypass()
1072 switch(tmpSC->SCp.phase) { in nspintr()
1124 if (((tmpSC->SCp.phase == PH_MSG_IN) || (tmpSC->SCp.phase == PH_MSG_OUT)) && in nspintr()
[all …]
/linux/Documentation/devicetree/bindings/mmc/
A Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
/linux/drivers/infiniband/hw/efa/
A Defa_com.c347 aq->sq.phase = !aq->sq.phase; in __efa_com_submit_admin_cmd()
438 u8 phase; in efa_com_handle_admin_completion() local
444 phase = aq->cq.phase; in efa_com_handle_admin_completion()
462 phase = !phase; in efa_com_handle_admin_completion()
469 aq->cq.phase = phase; in efa_com_handle_admin_completion()
843 phase = aenq->phase; in efa_com_aenq_intr_handler()
867 phase = !phase; in efa_com_aenq_intr_handler()
874 aenq->phase = phase; in efa_com_aenq_intr_handler()
1169 phase = eeq->phase; in efa_com_eq_comp_intr_handler()
1188 phase = !phase; in efa_com_eq_comp_intr_handler()
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/linux/tools/power/pm-graph/
A Dsleepgraph.py1519 return phase
1734 lp = phase
1759 phase += '*'
1775 return phase
2016 d = DevItem(0, phase, self.dmesg[phase]['list'][devname])
2590 phase = ''
2594 phase = p
2596 if not phase:
2621 self.phase = phase
4625 length = phase['end']-phase['start']
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/linux/drivers/leds/trigger/
A Dledtrig-heartbeat.c27 unsigned int phase; member
52 switch (heartbeat_data->phase) { in led_heartbeat_function()
65 heartbeat_data->phase++; in led_heartbeat_function()
71 heartbeat_data->phase++; in led_heartbeat_function()
77 heartbeat_data->phase++; in led_heartbeat_function()
84 heartbeat_data->phase = 0; in led_heartbeat_function()
140 heartbeat_data->phase = 0; in heartbeat_trig_activate()
/linux/drivers/scsi/
A DNCR5380.c1202 phase = PHASE_MSGOUT; in NCR5380_select()
1363 *phase = tmp & PHASE_MASK; in NCR5380_transfer_pio()
1365 *phase = PHASE_UNKNOWN; in NCR5380_transfer_pio()
1367 if (!c || (*phase == p)) in NCR5380_transfer_pio()
1451 phase = PHASE_MSGOUT; in do_abort()
1491 unsigned char p = *phase; in NCR5380_transfer_dma()
1497 *phase = tmp; in NCR5380_transfer_dma()
1700 old_phase = phase; in NCR5380_information_transfer()
1740 switch (phase) { in NCR5380_information_transfer()
1918 phase = PHASE_MSGIN; in NCR5380_information_transfer()
[all …]
/linux/drivers/scsi/arm/
A Dfas216.c275 phases[info->scsi.phase]) in fas216_drv_phase()
716 total = info->scsi.SCp.phase; in fas216_cleanuptransfer()
754 info->scsi.SCp.phase); in fas216_transfer()
888 info->scsi.phase); in fas216_disconnect_intr()
892 switch (info->scsi.phase) { in fas216_disconnect_intr()
900 info->scsi.phase = PHASE_IDLE; in fas216_disconnect_intr()
951 info->scsi.phase, cfis); in fas216_reselected_intr()
1356 switch (info->scsi.phase) { in fas216_busservice_intr()
1559 switch (info->scsi.phase) { in fas216_funcdone_intr()
1607 info->scsi.phase = PHASE_IDLE; in fas216_bus_reset()
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