/linux/drivers/net/phy/ |
A D | nxp-c45-tja11xx.c | 543 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp() 549 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp() 650 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable() 655 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable() 657 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable() 690 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt() 897 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays() 907 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays() 1041 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init() 1042 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init() [all …]
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A D | mediatek-ge.c | 27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in mtk_gephy_config_init() 40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); in mtk_gephy_config_init() 43 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); in mtk_gephy_config_init() 68 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); in mt7531_phy_config_init() 69 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); in mt7531_phy_config_init()
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A D | intel-xway.c | 255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init() 259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init() 272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init() 273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init() 274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init() 275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init() 276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init() 277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
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A D | dp83869.c | 272 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol() 278 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol() 284 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol() 296 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol() 302 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol() 307 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol() 696 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, in dp83869_configure_mode() 731 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode() 743 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode() 764 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode() [all …]
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A D | dp83tc811.c | 113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1, in dp83811_set_wol() 115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2, in dp83811_set_wol() 117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3, in dp83811_set_wol() 128 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol() 131 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol() 134 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol() 148 return phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
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A D | dp83867.c | 201 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol() 203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol() 205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol() 214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol() 216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, in dp83867_set_wol() 218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, in dp83867_set_wol() 240 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); in dp83867_set_wol() 757 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init() 766 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init() 811 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); in dp83867_config_init()
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A D | at803x.c | 440 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], in at803x_set_wol() 1485 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init() 1488 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init() 1600 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config() 1647 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in qca808x_config_init() 1812 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); in qca808x_cable_test_start() 1813 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); in qca808x_cable_test_start() 1814 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); in qca808x_cable_test_start() 1815 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); in qca808x_cable_test_start() 1816 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); in qca808x_cable_test_start() [all …]
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A D | dp83822.c | 138 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, in dp83822_set_wol() 140 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, in dp83822_set_wol() 142 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, in dp83822_set_wol() 153 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol() 156 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol() 159 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol() 173 return phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol() 582 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | in dp83822_resume()
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A D | micrel.c | 529 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); in ksz8061_config_init() 717 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values() 725 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, in ksz9031_center_flp_timing() 730 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, in ksz9031_center_flp_timing() 746 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, in ksz9031_enable_edpd() 784 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, in ksz9031_config_rgmii_delay() 790 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay() 798 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay() 806 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, in ksz9031_config_rgmii_delay() 959 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
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A D | marvell-88x2222.c | 81 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset() 202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line() 205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line() 208 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
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A D | aquantia_main.c | 257 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr() 262 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr() 267 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, in aqr_config_intr()
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A D | phy-c45.c | 113 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced() 117 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
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A D | marvell10g.c | 258 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config() 1177 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol() 1184 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol() 1191 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
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A D | aquantia_hwmon.c | 79 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
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A D | bcm-phy-lib.c | 384 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee() 403 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
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A D | phy-core.c | 562 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) in phy_write_mmd() function 572 EXPORT_SYMBOL(phy_write_mmd);
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A D | microchip.c | 329 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, in lan88xx_config_init()
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A D | adin.c | 287 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode() 314 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
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A D | phy.c | 1389 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); in phy_ethtool_set_eee()
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/linux/drivers/net/ethernet/realtek/ |
A D | r8169_phy_config.c | 601 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); in rtl8168e_1_hw_phy_config()
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A D | r8169_main.c | 1947 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); in rtl_enable_eee()
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/linux/drivers/net/usb/ |
A D | lan78xx.c | 2111 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8010, buf); in lan8835_fixup() 2131 phy_write_mmd(phydev, MDIO_MMD_WIS, 4, 0x0077); in ksz9031rnx_fixup() 2133 phy_write_mmd(phydev, MDIO_MMD_WIS, 5, 0x7777); in ksz9031rnx_fixup() 2135 phy_write_mmd(phydev, MDIO_MMD_WIS, 8, 0x1FF); in ksz9031rnx_fixup()
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/linux/include/linux/ |
A D | phy.h | 1123 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
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/linux/ |
A D | vmlinux.symvers | 5341 0x00000000 phy_write_mmd vmlinux EXPORT_SYMBOL
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A D | System.map | 35765 ffff8000109447f4 T phy_write_mmd
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