| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 943 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
954 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
955 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
956 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
957 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
959 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1202 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1682 const unsigned int pipe_idx, in dml31_rq_dlg_get_dlg_reg() argument
1706 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml31_rq_dlg_get_dlg_reg()
1712 pipe_idx, in dml31_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_31.h | 62 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 336 int i, pipe_idx; in dcn301_calculate_wm_and_dlg() local
371 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_calculate_wm_and_dlg()
375 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg()
376 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_calculate_wm_and_dlg()
379 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg()
380 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_calculate_wm_and_dlg()
382 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_calculate_wm_and_dlg()
383 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg()
384 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_calculate_wm_and_dlg()
385 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 1891 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1896 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1975 int pipe_idx = secondary_pipe->pipe_idx; in dcn20_split_stream_for_mpc() local
1981 secondary_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_mpc()
2822 pipe_idx++; in dcn20_validate_apply_pipe_split_flags()
2874 pipe_idx++; in dcn20_fast_validate_bw()
2883 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn20_fast_validate_bw()
2920 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn20_fast_validate_bw()
3153 pipe_idx++; in dcn20_calculate_dlg_params()
3178 pipe_idx, in dcn20_calculate_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 984 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
997 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
1309 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1320 pipe_idx, in dml_rq_dlg_get_dlg_params()
1324 pipe_idx, in dml_rq_dlg_get_dlg_params()
1344 pipe_idx); in dml_rq_dlg_get_dlg_params()
1348 pipe_idx); in dml_rq_dlg_get_dlg_params()
1836 const unsigned int pipe_idx, in dml30_rq_dlg_get_dlg_reg() argument
1868 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml30_rq_dlg_get_dlg_reg()
1873 pipe_idx, in dml30_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_30.h | 62 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 833 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1153 pipe_idx); in dml_rq_dlg_get_dlg_params()
1158 pipe_idx); in dml_rq_dlg_get_dlg_params()
1663 const unsigned int pipe_idx, in dml21_rq_dlg_get_dlg_reg() argument
1698 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml21_rq_dlg_get_dlg_reg()
1704 pipe_idx, in dml21_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_21.h | 66 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params() argument
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
1104 pipe_idx); in dml20_rq_dlg_get_dlg_params()
1108 pipe_idx); in dml20_rq_dlg_get_dlg_params()
1554 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_reg() argument
1586 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml20_rq_dlg_get_dlg_reg()
1591 pipe_idx, in dml20_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params() argument
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
1105 pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1109 pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1555 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_reg() argument
1587 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml20v2_rq_dlg_get_dlg_reg()
1592 pipe_idx, in dml20v2_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_20v2.h | 66 const unsigned int pipe_idx,
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| A D | display_rq_dlg_calc_20.h | 66 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc() argument
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.c | 1763 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1768 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1828 pipe->pipe_idx = old_index; in dcn30_find_split_pipe()
1837 pipe->pipe_idx = i; in dcn30_find_split_pipe()
1852 pipe->pipe_idx = i; in dcn30_find_split_pipe()
1873 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1946 pipe_idx++; in dcn30_internal_validate_bw()
2006 pipe_idx++; in dcn30_internal_validate_bw()
2132 int i, pipe_idx; in dcn30_calculate_wm_and_dlg_fp() local
2254 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 1104 int pipe_cnt, i, pipe_idx; in dcn21_calculate_wm() local
1123 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn21_calculate_wm()
1128 pipe_idx++; in dcn21_calculate_wm()
1141 if (pipe_cnt != pipe_idx) { in dcn21_calculate_wm()
1193 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
1235 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1252 pipe_idx++; in dcn21_fast_validate_bw()
1266 pipe_idx++; in dcn21_fast_validate_bw()
1275 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn21_fast_validate_bw()
1294 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 1173 pipe_ctx->pipe_idx, in resource_build_scaling_params()
1272 secondary_pipe->pipe_idx = i; in find_idle_secondary_pipe()
1372 split_pipe->pipe_idx = i; in acquire_first_split_pipe()
1426 if (pipe_idx >= 0) in dc_add_plane_to_context()
1763 pipe_ctx->pipe_idx = i; in acquire_first_free_pipe()
2070 pipe_ctx->pipe_idx = tg_inst; in acquire_resource_from_hw_enabled_state()
2102 int pipe_idx = -1; in resource_map_pool_resources() local
2113 if (pipe_idx < 0) in resource_map_pool_resources()
2118 if (pipe_idx < 0) in resource_map_pool_resources()
2123 if (pipe_idx < 0) in resource_map_pool_resources()
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| A D | dc_debug.c | 323 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) in context_timing_trace()
333 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) in context_timing_trace()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_trace.h | 382 TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,
386 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
389 __field(int, pipe_idx)
421 __entry->pipe_idx = pipe_idx;
455 __entry->pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_trace.h | 30 trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_lib.h | 55 const unsigned int pipe_idx,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| A D | dce110_clk_mgr.c | 148 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
241 pp_display_cfg->disp_configs[0].pipe_idx; in dce11_pplib_apply_display_requirements()
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| /linux/drivers/gpu/drm/amd/display/dc/calcs/ |
| A D | dcn_calcs.c | 311 input->src.hsplit_grp = pipe->pipe_idx; in pipe_ctx_to_e2e_pipe_params()
529 int pipe_idx = secondary_pipe->pipe_idx; in split_stream_across_pipes() local
536 secondary_pipe->pipe_idx = pipe_idx; in split_stream_across_pipes()
537 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
538 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
539 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
540 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
541 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
542 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 1860 int i, pipe_idx; in dcn31_calculate_wm_and_dlg_fp() local
1967 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
1971 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1972 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
1975 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1976 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1978 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
1979 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
1980 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
1981 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_hw_sequencer.c | 1466 pipe_ctx[pipe_ctx->pipe_idx];
1752 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
2046 uint32_t *pipe_idx) argument
2073 if (pipe_ctx->pipe_idx != underlay_idx) {
2074 *pipe_idx = i;
2112 uint32_t pipe_idx = 0; local
2114 if (should_enable_fbc(dc, context, &pipe_idx)) {
2118 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2822 pipe_ctx->pipe_idx,
2843 pipe_ctx->pipe_idx,
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_amdkfd_gfx_v9.c | 739 int pipe_idx; in get_wave_count() local
750 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
752 soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0); in get_wave_count()
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