/linux/drivers/gpu/drm/i915/ |
A D | i915_pci.c | 160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 181 .pipe_mask = BIT(PIPE_A), \ 223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 502 .pipe_mask = 0, /* legal, last one wins */ 511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 606 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 883 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), [all …]
|
A D | intel_device_info.c | 329 info->pipe_mask = 0; in intel_device_info_runtime_init() 333 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init() 340 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init() 344 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init() 348 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init() 354 info->pipe_mask &= ~BIT(PIPE_D); in intel_device_info_runtime_init()
|
A D | i915_irq.h | 70 u8 pipe_mask); 72 u8 pipe_mask);
|
A D | intel_device_info.h | 192 u8 pipe_mask; member
|
A D | i915_drv.h | 1744 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1746 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
|
A D | i915_irq.c | 3201 u8 pipe_mask) in gen8_irq_power_well_post_enable() argument 3216 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable() 3225 u8 pipe_mask) in gen8_irq_power_well_pre_disable() argument 3237 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
|
/linux/drivers/gpu/drm/i915/display/ |
A D | intel_ddi.c | 732 *pipe_mask = 0; in intel_ddi_get_encoder_pipes() 754 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes() 757 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes() 799 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes() 802 if (!*pipe_mask) in intel_ddi_get_encoder_pipes() 811 *pipe_mask); in intel_ddi_get_encoder_pipes() 812 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes() 840 u8 pipe_mask; in intel_ddi_get_hw_state() local 845 if (is_mst || !pipe_mask) in intel_ddi_get_hw_state() 1961 u8 pipe_mask; in intel_ddi_sanitize_encoder_pll_mapping() local [all …]
|
A D | intel_dpll_mgr.c | 199 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll() local 208 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll() 212 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll() 245 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll() local 268 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll() 299 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll() 312 shared_dpll[i].pipe_mask, in intel_find_shared_dpll() 341 if (shared_dpll[id].pipe_mask == 0) in intel_reference_shared_dpll() 347 shared_dpll[id].pipe_mask |= BIT(crtc->pipe); in intel_reference_shared_dpll() 4237 pll->state.pipe_mask = 0; in readout_dpll_hw_state() [all …]
|
A D | g4x_hdmi.c | 594 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init() 596 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init() 598 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
|
A D | intel_dpll_mgr.h | 245 u8 pipe_mask; member
|
A D | intel_display_types.h | 167 u8 pipe_mask; member 1767 INTEL_INFO(i915)->pipe_mask & BIT(pipe) && in intel_pipe_valid() 1782 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); in intel_get_crtc_for_pipe()
|
A D | g4x_dp.c | 1391 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init() 1393 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init() 1395 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
|
A D | intel_lvds.c | 923 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init() 925 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
|
A D | intel_crt.c | 1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init() 1051 crt->base.pipe_mask = ~0; in intel_crt_init()
|
A D | vlv_dsi.c | 1887 intel_encoder->pipe_mask = ~0; in vlv_dsi_init() 1889 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init() 1891 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
|
A D | intel_dvo.c | 524 intel_encoder->pipe_mask = ~0; in intel_dvo_init()
|
A D | intel_display.c | 8138 u8 pipe_mask; in verify_single_dpll_state() local 8160 pll->active_mask, pll->state.pipe_mask); in verify_single_dpll_state() 8165 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state() 8172 I915_STATE_WARN(pll->active_mask & pipe_mask, in verify_single_dpll_state() 8176 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state() 8178 pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state() 8198 u8 pipe_mask = BIT(crtc->pipe); in verify_shared_dpll_state() local 8201 I915_STATE_WARN(pll->active_mask & pipe_mask, in verify_shared_dpll_state() 8204 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, in verify_shared_dpll_state() 8206 pipe_name(crtc->pipe), pll->state.pipe_mask); in verify_shared_dpll_state() [all …]
|
A D | intel_display.h | 351 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
|
A D | intel_dp_mst.c | 915 intel_encoder->pipe_mask = ~0; in intel_dp_create_fake_mst_encoder()
|
A D | intel_tv.c | 1962 intel_encoder->pipe_mask = ~0; in intel_tv_init()
|
A D | icl_dsi.c | 2027 encoder->pipe_mask = ~0; in icl_dsi_init()
|
A D | intel_display_debugfs.c | 1105 pll->state.pipe_mask, pll->active_mask, yesno(pll->on)); in i915_shared_dplls_info()
|
A D | intel_sdvo.c | 2997 intel_sdvo->base.pipe_mask = ~0; in intel_sdvo_output_setup()
|
/linux/drivers/usb/renesas_usbhs/ |
A D | common.c | 276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local 278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
|
/linux/drivers/staging/media/atomisp/pci/ |
A D | sh_css.c | 10565 u32 pipe_mask = 0; local 10578 pipe_mask |= (1 << curr_pipe->config.mode); 10582 (((pipe_mask & (1 << IA_CSS_PIPE_MODE_PREVIEW)) || 10583 (pipe_mask & (1 << IA_CSS_PIPE_MODE_VIDEO))) && 10584 (pipe_mask & (1 << IA_CSS_PIPE_MODE_CAPTURE)) &&
|