| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 1462 stream_status->plane_count++; in dc_add_plane_to_context()
1515 for (i = 0; i < stream_status->plane_count; i++) { in dc_remove_plane_from_context()
1523 if (i == stream_status->plane_count) { in dc_remove_plane_from_context()
1528 stream_status->plane_count--; in dc_remove_plane_from_context()
1531 for (; i < stream_status->plane_count; i++) in dc_remove_plane_from_context()
1559 old_plane_count = stream_status->plane_count; in dc_rem_all_planes_for_stream()
1589 for (j = 0; j < set[i].plane_count; j++) in add_all_planes_for_stream()
1600 int plane_count, in dc_add_all_planes_for_stream() argument
1607 set.plane_count = plane_count; in dc_add_all_planes_for_stream()
1609 for (i = 0; i < plane_count; i++) in dc_add_all_planes_for_stream()
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| A D | dc.c | 1718 context->stream_status[i].plane_count, in dc_commit_state_no_check()
1755 context->stream_status[i].plane_count, in dc_commit_state_no_check()
2005 for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) in dc_copy_state()
2336 if (stream_status == NULL || stream_status->plane_count != surface_count) in check_update_surfaces_for_stream()
2974 dc, pipe_ctx->stream, stream_status->plane_count, context); in commit_planes_for_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_stream.h | 44 int plane_count; member
385 int plane_count,
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| A D | dc.h | 1107 uint8_t plane_count; member
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| /linux/drivers/media/platform/s5p-mfc/ |
| A D | s5p_mfc_dec.c | 902 unsigned int *plane_count, unsigned int psize[], in s5p_mfc_queue_setup() argument
913 *plane_count = 1; in s5p_mfc_queue_setup()
923 *plane_count = 2; in s5p_mfc_queue_setup()
937 *buf_count, *plane_count); in s5p_mfc_queue_setup()
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| A D | s5p_mfc_enc.c | 2375 unsigned int *buf_count, unsigned int *plane_count, in s5p_mfc_queue_setup() argument
2388 *plane_count = ctx->dst_fmt->num_planes; in s5p_mfc_queue_setup()
2390 *plane_count = MFC_ENC_CAP_PLANE_COUNT; in s5p_mfc_queue_setup()
2399 *plane_count = ctx->src_fmt->num_planes; in s5p_mfc_queue_setup()
2401 *plane_count = MFC_ENC_OUT_PLANE_COUNT; in s5p_mfc_queue_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_resource.c | 1219 if (context->stream_status[i].plane_count == 0) in dcn10_validate_global()
1222 if (context->stream_status[i].plane_count > 2) in dcn10_validate_global()
1225 if (context->stream_status[i].plane_count > 1) in dcn10_validate_global()
1228 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dcn10_validate_global()
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| A D | dcn10_hw_sequencer.c | 2925 if (context->stream_status[i].plane_count == 0) in dcn10_post_unlock_program_front_end()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| A D | clk_mgr.c | 84 total_plane_count += stream_status.plane_count; in clk_mgr_helper_get_active_plane_cnt()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_resource.c | 1053 if (context->stream_status[i].plane_count == 0) in dce110_validate_surface_sets()
1056 if (context->stream_status[i].plane_count > 2) in dce110_validate_surface_sets()
1059 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dce110_validate_surface_sets()
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| /linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| A D | dce100_resource.c | 867 if (context->stream_status[i].plane_count == 0) in dce100_validate_surface_sets()
870 if (context->stream_status[i].plane_count > 1) in dce100_validate_surface_sets()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 2650 int plane_count = 0; in dcn20_validate_apply_pipe_split_flags() local
2680 ++plane_count; in dcn20_validate_apply_pipe_split_flags()
2682 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
2726 bool split4mpc = context->stream_count == 1 && plane_count == 1 in dcn20_validate_apply_pipe_split_flags()
3076 int plane_count; in decide_zstate_support() local
3079 plane_count = 0; in decide_zstate_support()
3082 plane_count++; in decide_zstate_support()
3091 if (plane_count == 0) in decide_zstate_support()
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| A D | dcn20_hwseq.c | 1799 if (dc->current_state->stream_status[0].plane_count == 1 && in dcn20_post_unlock_program_front_end()
1800 context->stream_status[0].plane_count > 1) { in dcn20_post_unlock_program_front_end()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_hwseq.c | 751 if (dc->current_state->stream_status[i].plane_count) in dcn30_apply_idle_power_optimizations()
789 dc->current_state->stream_status[0].plane_count == 1 && in dcn30_apply_idle_power_optimizations()
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| /linux/drivers/gpu/drm/amd/display/dc/dce112/ |
| A D | dce112_resource.c | 996 if (context->stream_status[i].plane_count == 0) in dce112_validate_surface_sets()
999 if (context->stream_status[i].plane_count > 1) in dce112_validate_surface_sets()
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_resource.c | 896 if (context->stream_status[i].plane_count == 0) in dce60_validate_surface_sets()
899 if (context->stream_status[i].plane_count > 1) in dce60_validate_surface_sets()
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| /linux/drivers/gpu/drm/amd/display/dc/dce80/ |
| A D | dce80_resource.c | 901 if (context->stream_status[i].plane_count == 0) in dce80_validate_surface_sets()
904 if (context->stream_status[i].plane_count > 1) in dce80_validate_surface_sets()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm.c | 2255 if (acrtc && state->stream_status[i].plane_count != 0) { in dm_gpureset_toggle_interrupts()
2502 for (m = 0; m < dc_state->stream_status->plane_count; m++) { in dm_gpureset_commit_state()
2510 dc_state->stream_status->plane_count, in dm_gpureset_commit_state()
2598 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { in dm_resume()
9677 WARN_ON(!status->plane_count); in amdgpu_dm_atomic_commit_tail()
9684 for (j = 0; j < status->plane_count; j++) in amdgpu_dm_atomic_commit_tail()
9691 status->plane_count, in amdgpu_dm_atomic_commit_tail()
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