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Searched refs:port_clock (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
A Dintel_ddi_buf_trans.c1220 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1249 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1274 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1301 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1330 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1384 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1400 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1431 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1477 if (crtc_state->port_clock > 270000) in adls_get_combo_buf_trans_dp()
1491 if (crtc_state->port_clock > 540000) in adls_get_combo_buf_trans_edp()
[all …]
A Dintel_ddi.c218 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
255 switch (port_clock) { in ddi_buf_phy_link_rate()
273 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
333 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
1029 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1227 if (crtc_state->port_clock < 300000) in icl_mg_phy_set_signal_levels()
1238 if (crtc_state->port_clock <= 500000) { in icl_mg_phy_set_signal_levels()
1248 if (crtc_state->port_clock <= 500000) { in icl_mg_phy_set_signal_levels()
2402 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2544 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
[all …]
A Dg4x_dp.c93 if (pipe_config->port_clock == divisor[i].clock) { in g4x_dp_set_clock()
112 pipe_config->port_clock, in intel_dp_prepare()
219 pipe_config->port_clock); in ilk_edp_pll_on()
223 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
390 pipe_config->port_clock = 162000; in intel_dp_get_config()
392 pipe_config->port_clock = 270000; in intel_dp_get_config()
396 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
A Dintel_dp_link_training.c654 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
868 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
886 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
1059 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1077 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
A Dintel_dpll.c770 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1115 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1180 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1201 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1245 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1282 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1319 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1358 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1562 if (crtc_state->port_clock == 162000 || in vlv_prepare_pll()
A Dintel_audio.c132 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
289 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
536 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
574 link_clk = crtc_state->port_clock; in calc_samples_room()
873 crtc_state->port_clock, in intel_audio_codec_enable()
A Dintel_dp.h74 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
A Dintel_dpio_phy.c916 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
918 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
920 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
922 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
A Dintel_snps_phy.c780 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) in intel_mpllb_calc_state()
788 crtc_state->port_clock); in intel_mpllb_calc_state()
798 if (crtc_state->port_clock <= tables[i]->clock) { in intel_mpllb_calc_state()
A Dintel_dp.c121 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
1033 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1035 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1222 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1356 pipe_config->port_clock = limits->max_rate; in intel_dp_dsc_compute_config()
1372 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1520 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1528 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1539 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1838 pipe_config->port_clock, in intel_dp_compute_config()
[all …]
A Dintel_dpll_mgr.c867 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_get_dpll()
932 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
989 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_get_dpll()
1551 if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1656 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2092 crtc_state->port_clock, in bxt_ddi_hdmi_pll_dividers()
2113 int clock = crtc_state->port_clock; in bxt_ddi_dp_pll_dividers()
2132 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2509 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2592 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
[all …]
A Dintel_dp_mst.c64 crtc_state->port_clock = limits->max_rate; in intel_dp_mst_compute_link_config()
77 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
94 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
A Dg4x_hdmi.c121 dotclock = pipe_config->port_clock * 2 / 3; in intel_hdmi_get_config()
123 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
A Dintel_drrs.c82 pipe_config->port_clock, &pipe_config->dp_m2_n2, in intel_drrs_compute_config()
A Dintel_crt.c140 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
446 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
A Dintel_dvo.c184 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
A Dintel_hdmi.c2074 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); in intel_hdmi_compute_clock()
2088 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, in intel_hdmi_compute_clock()
2092 crtc_state->port_clock); in intel_hdmi_compute_clock()
2230 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
A Dintel_display.c4299 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
5793 int port_clock; in i9xx_crtc_clock_get() local
5835 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
5837 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
5866 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
5874 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
6799 pipe_config->port_clock, in intel_dump_pipe_config()
7133 pipe_config->port_clock = 0; in intel_modeset_pipe_config()
7163 if (!pipe_config->port_clock) in intel_modeset_pipe_config()
7775 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); in intel_pipe_config_compare()
[all …]
A Dintel_tv.c1119 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1207 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
A Dintel_cdclk.c2125 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2152 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2387 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
A Dintel_lvds.c154 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
A Dintel_display_types.h1080 int port_clock; member
A Dintel_fdi.c220 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
A Dintel_sdvo.c1257 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1685 dotclock = pipe_config->port_clock; in intel_sdvo_get_config()
A Dvlv_dsi.c1275 pipe_config->port_clock = pclk; in intel_dsi_get_config()

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