Searched refs:pp_smu_status (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_pp_smu.h | 60 enum pp_smu_status { enum
173 enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
197 enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
202 enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
217 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
228 enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,
279 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
282 enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
298 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
302 enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
[all …]
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_pp_smu.c | 607 static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, in pp_nv_set_wm_ranges()
621 static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) in pp_nv_set_display_count()
638 static enum pp_smu_status
656 static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq( in pp_nv_set_hard_min_dcefclk_by_freq()
680 static enum pp_smu_status
704 static enum pp_smu_status pp_nv_set_pstate_handshake_support( in pp_nv_set_pstate_handshake_support()
721 static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, in pp_nv_set_voltage_by_freq()
757 static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks( in pp_nv_get_maximum_sustainable_clocks()
774 static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, in pp_nv_get_uclk_dpm_states()
793 static enum pp_smu_status pp_rn_get_dpm_clock_table( in pp_rn_get_dpm_clock_table()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 943 enum pp_smu_status status = 0; in rn_clk_mgr_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 3677 enum pp_smu_status status; in init_soc_bounding_box()
|
Completed in 15 milliseconds