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Searched refs:ppll_div_3 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/video/fbdev/aty/
A Dradeon_base.c1341 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()
1362 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
1411 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
1412 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1630 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1634 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); in radeon_calc_pll_regs()
1698 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | in radeonfb_set_par()
A Dradeonfb.h236 u32 ppll_div_3; member
/linux/drivers/gpu/drm/radeon/
A Dradeon_legacy_tv.c873 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) in radeon_legacy_tv_adjust_pll1() argument
886 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); in radeon_legacy_tv_adjust_pll1()
A Dradeon_mode.h967 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);

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