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Searched refs:ppll_ref_div (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/video/fbdev/aty/
A Dradeon_base.c1342 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1361 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1396 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
1400 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1404 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
1408 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1629 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
1700 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()
A Dradeonfb.h237 u32 ppll_ref_div; member
/linux/drivers/gpu/drm/radeon/
A Dradeon_legacy_tv.c872 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, in radeon_legacy_tv_adjust_pll1() argument
884 *ppll_ref_div = const_ptr->crtcPLL_M; in radeon_legacy_tv_adjust_pll1()
A Dradeon_mode.h966 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,

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