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Searched refs:prate (Results 1 – 25 of 125) sorted by relevance

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/linux/drivers/gpu/drm/mcde/
A Dmcde_clk_div.c44 unsigned long *prate, bool set_parent) in mcde_clk_div_choose_div() argument
58 this_prate = *prate; in mcde_clk_div_choose_div()
69 *prate = best_prate; in mcde_clk_div_choose_div()
74 unsigned long *prate) in mcde_clk_div_round_rate() argument
76 int div = mcde_clk_div_choose_div(hw, rate, prate, true); in mcde_clk_div_round_rate()
78 return DIV_ROUND_UP_ULL(*prate, div); in mcde_clk_div_round_rate()
82 unsigned long prate) in mcde_clk_div_recalc_rate() argument
95 return DIV_ROUND_UP_ULL(prate, 2); in mcde_clk_div_recalc_rate()
99 return prate; in mcde_clk_div_recalc_rate()
105 return DIV_ROUND_UP_ULL(prate, div); in mcde_clk_div_recalc_rate()
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/linux/drivers/clk/meson/
A Dsclk-div.c42 unsigned long prate, int maxdiv) in sclk_div_getdiv() argument
44 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); in sclk_div_getdiv()
50 unsigned long *prate, in sclk_div_bestdiv() argument
64 return sclk_div_getdiv(hw, rate, *prate, maxdiv); in sclk_div_bestdiv()
78 if (rate * i == *prate) in sclk_div_bestdiv()
94 *prate = best_parent; in sclk_div_bestdiv()
100 unsigned long *prate) in sclk_div_round_rate() argument
106 div = sclk_div_bestdiv(hw, rate, prate, sclk); in sclk_div_round_rate()
108 return DIV_ROUND_UP_ULL((u64)*prate, div); in sclk_div_round_rate()
167 unsigned long prate) in sclk_div_set_rate() argument
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A Dclk-cpu-dyndiv.c20 unsigned long prate) in meson_clk_cpu_dyndiv_recalc_rate() argument
25 return divider_recalc_rate(hw, prate, in meson_clk_cpu_dyndiv_recalc_rate()
32 unsigned long *prate) in meson_clk_cpu_dyndiv_round_rate() argument
37 return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0); in meson_clk_cpu_dyndiv_round_rate()
/linux/drivers/clk/spear/
A Dclk-frac-synth.c44 static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, in frac_calc_rate() argument
50 prate /= 10000; in frac_calc_rate()
51 prate <<= 14; in frac_calc_rate()
52 prate /= (2 * rtbl[index].div); in frac_calc_rate()
53 prate *= 10000; in frac_calc_rate()
55 return prate; in frac_calc_rate()
59 unsigned long *prate) in clk_frac_round_rate() argument
64 return clk_round_rate_index(hw, drate, *prate, frac_calc_rate, in clk_frac_round_rate()
96 unsigned long prate) in clk_frac_set_rate() argument
103 clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, in clk_frac_set_rate()
A Dclk-vco-pll.c72 unsigned long rate = prate; in pll_calc_rate()
85 unsigned long *prate, int *index) in clk_pll_round_rate_index() argument
92 if (!prate) { in clk_pll_round_rate_index()
99 vco_prev_rate = *prate; in clk_pll_round_rate_index()
106 *prate = vco_prev_rate; in clk_pll_round_rate_index()
117 unsigned long *prate) in clk_pll_round_rate() argument
145 unsigned long prate) in clk_pll_set_rate() argument
175 unsigned long prate, int index) in vco_calc_rate() argument
179 return pll_calc_rate(vco->rtbl, prate, index, NULL); in vco_calc_rate()
183 unsigned long *prate) in clk_vco_round_rate() argument
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A Dclk-gpt-synth.c34 static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, in gpt_calc_rate() argument
40 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); in gpt_calc_rate()
42 return prate; in gpt_calc_rate()
46 unsigned long *prate) in clk_gpt_round_rate() argument
51 return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate, in clk_gpt_round_rate()
81 unsigned long prate) in clk_gpt_set_rate() argument
88 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt, in clk_gpt_set_rate()
A Dclk-aux-synth.c44 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, in aux_calc_rate() argument
51 return (((prate / 10000) * rtbl[index].xscale) / in aux_calc_rate()
56 unsigned long *prate) in clk_aux_round_rate() argument
61 return clk_round_rate_index(hw, drate, *prate, aux_calc_rate, in clk_aux_round_rate()
100 unsigned long prate) in clk_aux_set_rate() argument
107 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt, in clk_aux_set_rate()
/linux/drivers/clk/renesas/
A Drcar-gen3-cpg.c70 unsigned long prate; in cpg_pll_clk_determine_rate() local
72 prate = req->best_parent_rate * pll_clk->fixed_mult; in cpg_pll_clk_determine_rate()
73 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_clk_determine_rate()
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
81 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
194 unsigned long rate, prate; in cpg_z_clk_determine_rate() local
199 prate = zclk->max_rate; in cpg_z_clk_determine_rate()
202 prate = rate; in cpg_z_clk_determine_rate()
205 prate * zclk->fixed_div); in cpg_z_clk_determine_rate()
207 prate = req->best_parent_rate / zclk->fixed_div; in cpg_z_clk_determine_rate()
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A Dclk-div6.c106 unsigned long prate, calc_rate, diff, best_rate, best_prate; in cpg_div6_clock_determine_rate() local
117 prate = clk_hw_get_rate(parent); in cpg_div6_clock_determine_rate()
118 if (!prate) in cpg_div6_clock_determine_rate()
121 min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL); in cpg_div6_clock_determine_rate()
122 max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64; in cpg_div6_clock_determine_rate()
126 div = cpg_div6_clock_calc_div(req->rate, prate); in cpg_div6_clock_determine_rate()
128 calc_rate = prate / div; in cpg_div6_clock_determine_rate()
134 best_prate = prate; in cpg_div6_clock_determine_rate()
A Dr8a779a0-cpg-mssr.c315 unsigned long rate, prate; in cpg_z_clk_determine_rate() local
320 prate = zclk->max_rate; in cpg_z_clk_determine_rate()
323 prate = rate; in cpg_z_clk_determine_rate()
326 prate * zclk->fixed_div); in cpg_z_clk_determine_rate()
328 prate = req->best_parent_rate / zclk->fixed_div; in cpg_z_clk_determine_rate()
329 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); in cpg_z_clk_determine_rate()
330 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); in cpg_z_clk_determine_rate()
334 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
337 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
/linux/drivers/clk/qcom/
A Dclk-alpha-pll.c455 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); in alpha_pll_calc_rate()
582 unsigned long prate, in __clk_alpha_pll_set_rate() argument
621 unsigned long prate) in clk_alpha_pll_set_rate() argument
628 unsigned long prate) in clk_alpha_pll_hwfsm_set_rate() argument
662 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); in alpha_huayra_pll_calc_rate()
797 unsigned long *prate) in alpha_pll_huayra_round_rate() argument
986 unsigned long *prate) in clk_alpha_pll_postdiv_round_rate() argument
1197 unsigned long prate) in alpha_pll_fabia_set_rate() argument
1340 unsigned long *prate) in clk_trion_pll_postdiv_round_rate() argument
1746 unsigned long prate) in alpha_pll_lucid_5lpe_set_rate() argument
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A Dclk-regmap-divider.c19 unsigned long *prate) in div_round_ro_rate() argument
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
34 unsigned long *prate) in div_round_rate() argument
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
A Dclk-regmap-mux-div.c125 unsigned long prate, u32 src) in __mux_div_set_rate_and_parent() argument
187 unsigned long rate, unsigned long prate) in mux_div_set_rate() argument
191 return __mux_div_set_rate_and_parent(hw, rate, prate, md->src); in mux_div_set_rate()
195 unsigned long prate, u8 index) in mux_div_set_rate_and_parent() argument
199 return __mux_div_set_rate_and_parent(hw, rate, prate, in mux_div_set_rate_and_parent()
203 static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) in mux_div_recalc_rate() argument
/linux/drivers/rtc/
A Drtc-ac100.c120 unsigned long prate) in ac100_clkout_recalc_rate() argument
128 if (prate != AC100_RTC_32K_RATE) { in ac100_clkout_recalc_rate()
131 prate = divider_recalc_rate(hw, prate, div, in ac100_clkout_recalc_rate()
138 return divider_recalc_rate(hw, prate, div, NULL, in ac100_clkout_recalc_rate()
144 unsigned long prate) in ac100_clkout_round_rate() argument
149 if (prate == AC100_RTC_32K_RATE) in ac100_clkout_round_rate()
178 unsigned long tmp, prate; in ac100_clkout_determine_rate() local
200 prate = clk_hw_get_rate(parent); in ac100_clkout_determine_rate()
223 unsigned long prate) in ac100_clkout_set_rate() argument
230 prate, NULL, AC100_CLKOUT_DIV_WIDTH, in ac100_clkout_set_rate()
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/linux/drivers/clk/x86/
A Dclk-cgu.c153 unsigned long *prate) in lgm_clk_divider_round_rate() argument
163 unsigned long prate) in lgm_clk_divider_set_rate() argument
423 u64 prate; in lgm_clk_ddiv_recalc_rate() local
431 prate = (u64)parent_rate; in lgm_clk_ddiv_recalc_rate()
432 do_div(prate, div0); in lgm_clk_ddiv_recalc_rate()
433 do_div(prate, div1); in lgm_clk_ddiv_recalc_rate()
437 prate *= ddiv->mult; in lgm_clk_ddiv_recalc_rate()
440 return prate; in lgm_clk_ddiv_recalc_rate()
532 unsigned long *prate) in lgm_clk_ddiv_round_rate() argument
550 return *prate; in lgm_clk_ddiv_round_rate()
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A Dclk-cgu-pll.c24 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
29 rate64 = prate; in lgm_pll_calc_rate()
39 static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) in lgm_pll_recalc_rate() argument
54 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
/linux/drivers/clk/samsung/
A Dclk-cpu.c106 unsigned long drate, unsigned long *prate) in exynos_cpuclk_round_rate() argument
109 *prate = clk_hw_round_rate(parent, drate); in exynos_cpuclk_round_rate()
110 return *prate; in exynos_cpuclk_round_rate()
159 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
160 if (cfg_data->prate == 0) in exynos_cpuclk_pre_rate_change()
236 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_post_rate_change()
237 if (cfg_data->prate == 0) in exynos_cpuclk_post_rate_change()
287 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos5433_cpuclk_pre_rate_change()
288 if (cfg_data->prate == 0) in exynos5433_cpuclk_pre_rate_change()
482 for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; ) in samsung_clk_register_cpu()
/linux/drivers/clk/
A Dclk-vt8500.c132 unsigned long *prate) in vt8500_dclk_round_rate() argument
140 divisor = *prate / rate; in vt8500_dclk_round_rate()
143 if (rate * divisor < *prate) in vt8500_dclk_round_rate()
154 return *prate / divisor; in vt8500_dclk_round_rate()
598 unsigned long *prate) in vtwm_pll_round_rate() argument
607 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1); in vtwm_pll_round_rate()
609 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); in vtwm_pll_round_rate()
612 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); in vtwm_pll_round_rate()
614 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
619 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
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A Dclk-lmk04832.c371 unsigned long prate) in lmk04832_vco_recalc_rate() argument
466 div = gcd(rate, prate); in lmk04832_calc_pll2_params()
469 pll2_r = DIV_ROUND_CLOSEST(prate, div); in lmk04832_calc_pll2_params()
491 unsigned long *prate) in lmk04832_vco_round_rate() argument
515 unsigned long prate) in lmk04832_vco_set_rate() argument
870 unsigned long prate) in lmk04832_sclk_recalc_rate() argument
888 unsigned long *prate) in lmk04832_sclk_round_rate() argument
909 unsigned long prate) in lmk04832_sclk_set_rate() argument
1043 unsigned long prate) in lmk04832_dclk_recalc_rate() argument
1069 unsigned long *prate) in lmk04832_dclk_round_rate() argument
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A Dclk-divider.c385 unsigned long rate, unsigned long *prate, in divider_round_rate_parent() argument
391 .best_parent_rate = *prate, in divider_round_rate_parent()
400 *prate = req.best_parent_rate; in divider_round_rate_parent()
407 unsigned long rate, unsigned long *prate, in divider_ro_round_rate_parent() argument
413 .best_parent_rate = *prate, in divider_ro_round_rate_parent()
422 *prate = req.best_parent_rate; in divider_ro_round_rate_parent()
429 unsigned long *prate) in clk_divider_round_rate() argument
440 return divider_ro_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
445 return divider_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
/linux/drivers/gpu/drm/pl111/
A Dpl111_display.c445 unsigned long *prate, bool set_parent) in pl111_clk_div_choose_div() argument
459 this_prate = *prate; in pl111_clk_div_choose_div()
470 *prate = best_prate; in pl111_clk_div_choose_div()
475 unsigned long *prate) in pl111_clk_div_round_rate() argument
477 int div = pl111_clk_div_choose_div(hw, rate, prate, true); in pl111_clk_div_round_rate()
479 return DIV_ROUND_UP_ULL(*prate, div); in pl111_clk_div_round_rate()
483 unsigned long prate) in pl111_clk_div_recalc_rate() argument
491 return prate; in pl111_clk_div_recalc_rate()
498 return DIV_ROUND_UP_ULL(prate, div); in pl111_clk_div_recalc_rate()
502 unsigned long prate) in pl111_clk_div_set_rate() argument
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/linux/drivers/clk/axs10x/
A Di2s_pll_clock.c89 static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate) in i2s_pll_get_cfg() argument
91 switch (prate) { in i2s_pll_get_cfg()
115 unsigned long *prate) in i2s_pll_round_rate() argument
118 const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate); in i2s_pll_round_rate()
122 dev_err(clk->dev, "invalid parent rate=%ld\n", *prate); in i2s_pll_round_rate()
/linux/drivers/clk/rockchip/
A Dclk-pll.c164 unsigned long prate) in rockchip_rk3036_pll_recalc_rate() argument
168 u64 rate64 = prate; in rockchip_rk3036_pll_recalc_rate()
177 u64 frac_rate64 = prate * cur.frac; in rockchip_rk3036_pll_recalc_rate()
249 unsigned long prate) in rockchip_rk3036_pll_set_rate() argument
401 unsigned long prate) in rockchip_rk3066_pll_recalc_rate() argument
405 u64 rate64 = prate; in rockchip_rk3066_pll_recalc_rate()
412 return prate; in rockchip_rk3066_pll_recalc_rate()
484 unsigned long prate) in rockchip_rk3066_pll_set_rate() argument
646 unsigned long prate) in rockchip_rk3399_pll_recalc_rate() argument
650 u64 rate64 = prate; in rockchip_rk3399_pll_recalc_rate()
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/linux/drivers/clk/imx/
A Dclk-pllv3.c120 unsigned long *prate) in clk_pllv3_round_rate() argument
122 unsigned long parent_rate = *prate; in clk_pllv3_round_rate()
168 unsigned long *prate) in clk_pllv3_sys_round_rate() argument
170 unsigned long parent_rate = *prate; in clk_pllv3_sys_round_rate()
229 unsigned long *prate) in clk_pllv3_av_round_rate() argument
231 unsigned long parent_rate = *prate; in clk_pllv3_av_round_rate()
358 unsigned long *prate) in clk_pllv3_vf610_round_rate() argument
360 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate); in clk_pllv3_vf610_round_rate()
362 return clk_pllv3_vf610_mf_to_rate(*prate, mf); in clk_pllv3_vf610_round_rate()
/linux/drivers/gpu/drm/atmel-hlcdc/
A Datmel_hlcdc_crtc.c73 unsigned long prate; in atmel_hlcdc_crtc_mode_set_nofb() local
102 prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); in atmel_hlcdc_crtc_mode_set_nofb()
105 prate *= 2; in atmel_hlcdc_crtc_mode_set_nofb()
110 div = DIV_ROUND_UP(prate, mode_rate); in atmel_hlcdc_crtc_mode_set_nofb()
116 prate /= 2; in atmel_hlcdc_crtc_mode_set_nofb()
117 div = DIV_ROUND_UP(prate, mode_rate); in atmel_hlcdc_crtc_mode_set_nofb()
121 int div_low = prate / mode_rate; in atmel_hlcdc_crtc_mode_set_nofb()
124 (10 * (prate / div_low - mode_rate) < in atmel_hlcdc_crtc_mode_set_nofb()
125 (mode_rate - prate / div))) in atmel_hlcdc_crtc_mode_set_nofb()

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