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Searched refs:rFPGA0_RFMOD (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/staging/rtl8712/
A Drtl871x_mp.c349 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); in r8712_SwitchBandwidth()
359 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); in r8712_SwitchBandwidth()
504 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) in r8712_SetSingleCarrierTx()
542 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); in r8712_SetSingleToneTx()
551 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); in r8712_SetSingleToneTx()
552 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleToneTx()
567 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { in r8712_SetCarrierSuppressionTx()
569 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, in r8712_SetCarrierSuppressionTx()
608 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { in SetCCKContinuousTx()
610 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); in SetCCKContinuousTx()
[all …]
A Drtl871x_mp_phy_regdef.h85 #define rFPGA0_RFMOD 0x800 /*RF mode & CCK TxSC RF macro
/linux/drivers/staging/rtl8192u/
A Dr819xU_phyreg.h8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
A Dr819xU_phy.c784 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in rtl8192_BB_Config_ParaFile()
1501 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in rtl8192_SetBWModeWorkItem()
1531 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in rtl8192_SetBWModeWorkItem()
A Dr8192U_core.c2788 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl8192_adapter_start()
2789 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl8192_adapter_start()
/linux/drivers/staging/rtl8723bs/hal/
A Drtl8723b_phycfg.c639 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_PostSetBwMode8723B()
648 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_PostSetBwMode8723B()
/linux/drivers/staging/r8188eu/hal/
A Drtl8188e_phycfg.c799 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode92C()
804 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode92C()
A DHalPhyRf_8188e.c813 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD in phy_IQCalibrate_8188E()
836 ODM_SetBBReg(dm_odm, rFPGA0_RFMOD, BIT(24), 0x00); in phy_IQCalibrate_8188E()
A Dusb_halinit.c575 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
576 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
/linux/drivers/staging/rtl8192e/rtl8192e/
A Dr8192E_phy.c552 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in _rtl92e_bb_config_para_file()
1192 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in _rtl92e_set_bw_mode_work_item()
1207 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in _rtl92e_set_bw_mode_work_item()
A Dr8192E_phyreg.h47 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
A Dr8192E_dev.c855 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl92e_start_adapter()
856 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl92e_start_adapter()
/linux/drivers/staging/rtl8723bs/include/
A DHal8192CPhyReg.h92 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ macro
/linux/drivers/staging/r8188eu/include/
A DHal8188EPhyReg.h54 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ macro

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