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Searched refs:rFPGA0_XAB_RFInterfaceSW (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/staging/rtl8192u/
A Dr819xU_phyreg.h28 #define rFPGA0_XAB_RFInterfaceSW 0x870 macro
A Dr819xU_phy.c549 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl8192_InitBBRFRegDef()
551 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl8192_InitBBRFRegDef()
/linux/drivers/staging/rtl8723bs/hal/
A Drtl8723b_phycfg.c311 …pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()
312 …pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()
A DHalPhyRf_8723B.c1361 rFPGA0_XAB_RFInterfaceSW, in phy_IQCalibrate_8723B()
/linux/drivers/staging/r8188eu/hal/
A DHalPhyRf_8188e.c812 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, in phy_IQCalibrate_8188E()
841 ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01); in phy_IQCalibrate_8188E()
842 ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01); in phy_IQCalibrate_8188E()
A Drtl8188e_phycfg.c393 …pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()
394 …pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()
/linux/drivers/staging/rtl8192e/rtl8192e/
A Dr8192E_phyreg.h73 #define rFPGA0_XAB_RFInterfaceSW 0x870 macro
A Dr8192E_phy.c382 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()
383 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()
/linux/drivers/staging/rtl8712/
A Drtl871x_mp_phy_regdef.h116 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Ctrl */ macro
/linux/drivers/staging/rtl8723bs/include/
A DHal8192CPhyReg.h127 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ macro
/linux/drivers/staging/r8188eu/include/
A DHal8188EPhyReg.h81 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ macro

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