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Searched refs:rdmsr (Results 1 – 25 of 78) sorted by relevance

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/linux/tools/testing/selftests/kvm/lib/x86_64/
A Dvmx.c144 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); in prepare_for_vmx_operation()
145 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); in prepare_for_vmx_operation()
149 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); in prepare_for_vmx_operation()
150 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); in prepare_for_vmx_operation()
163 feature_control = rdmsr(MSR_IA32_FEAT_CTL); in prepare_for_vmx_operation()
239 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | in init_vmcs_control_fields()
277 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); in init_vmcs_host_state()
279 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); in init_vmcs_host_state()
282 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); in init_vmcs_host_state()
289 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); in init_vmcs_host_state()
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A Dapic.c13 rdmsr(MSR_IA32_APICBASE) & in apic_disable()
19 uint64_t val = rdmsr(MSR_IA32_APICBASE); in xapic_enable()
25 rdmsr(MSR_IA32_APICBASE) | MSR_IA32_APICBASE_ENABLE); in xapic_enable()
41 wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) | in x2apic_enable()
A Dsvm.c83 efer = rdmsr(MSR_EFER); in generic_svm_setup()
98 save->efer = rdmsr(MSR_EFER); in generic_svm_setup()
105 save->g_pat = rdmsr(MSR_IA32_CR_PAT); in generic_svm_setup()
106 save->dbgctl = rdmsr(MSR_IA32_DEBUGCTLMSR); in generic_svm_setup()
/linux/drivers/cpufreq/
A Dlongrun.c39 rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi); in longrun_get_policy()
46 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); in longrun_get_policy()
95 rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi); in longrun_set_policy()
107 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); in longrun_set_policy()
180 rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi); in longrun_determine_freqs()
182 rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi); in longrun_determine_freqs()
187 rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi); in longrun_determine_freqs()
204 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); in longrun_determine_freqs()
A Dspeedstep-lib.c75 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); in pentium3_get_frequency()
112 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); in pentiumM_get_frequency()
135 rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp); in pentium_core_get_frequency()
160 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); in pentium_core_get_frequency()
189 rdmsr(0x2c, msr_lo, msr_hi); in pentium4_get_frequency()
345 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); in speedstep_detect_processor()
358 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); in speedstep_detect_processor()
A De_powersaver.c103 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_get()
115 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
119 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
131 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
143 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
199 rdmsr(0x1153, lo, hi); in eps_cpu_init()
204 rdmsr(0x1154, lo, hi); in eps_cpu_init()
241 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_cpu_init()
/linux/arch/x86/kernel/cpu/mtrr/
A Dgeneric.c56 rdmsr(MSR_AMD64_SYSCFG, lo, hi); in k8_check_syscfg_dram_mod_en()
342 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); in get_fixed_ranges()
470 rdmsr(MSR_MTRRcap, lo, dummy); in get_mtrr_state()
478 rdmsr(MSR_MTRRdefType, lo, dummy); in get_mtrr_state()
486 rdmsr(MSR_K8_TOP_MEM2, low, high); in get_mtrr_state()
542 rdmsr(msr, lo, hi); in set_fixed_range()
591 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); in generic_get_mtrr()
601 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); in generic_get_mtrr()
662 rdmsr(MTRRphysBase_MSR(index), lo, hi); in set_mtrr_var_ranges()
671 rdmsr(MTRRphysMask_MSR(index), lo, hi); in set_mtrr_var_ranges()
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A Damd.c15 rdmsr(MSR_K6_UWCCR, low, high); in amd_get_mtrr()
67 rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
/linux/arch/x86/kernel/cpu/mce/
A Dp5.c29 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); in pentium_machine_check()
30 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); in pentium_machine_check()
58 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); in intel_p5_mcheck_init()
59 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); in intel_p5_mcheck_init()
/linux/tools/testing/selftests/kvm/x86_64/
A Dhyperv_clock.c56 tsc_freq = rdmsr(HV_X64_MSR_TSC_FREQUENCY); in check_tsc_msr_rdtsc()
61 t1 = rdmsr(HV_X64_MSR_TIME_REF_COUNT); in check_tsc_msr_rdtsc()
64 t2 = rdmsr(HV_X64_MSR_TIME_REF_COUNT); in check_tsc_msr_rdtsc()
88 r1 = rdmsr(HV_X64_MSR_TIME_REF_COUNT); in check_tsc_msr_tsc_page()
95 r2 = rdmsr(HV_X64_MSR_TIME_REF_COUNT); in check_tsc_msr_tsc_page()
A Dvmx_preemption_timer_test.c88 basic.val = rdmsr(MSR_IA32_VMX_BASIC); in l1_guest_code()
89 ctrl_pin_rev.val = rdmsr(basic.ctrl ? MSR_IA32_VMX_TRUE_PINBASED_CTLS in l1_guest_code()
91 ctrl_exit_rev.val = rdmsr(basic.ctrl ? MSR_IA32_VMX_TRUE_EXIT_CTLS in l1_guest_code()
112 vmx_pt_rate = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; in l1_guest_code()
A Duserspace_msr_exit_test.c310 GUEST_ASSERT(rdmsr(MSR_SYSCALL_MASK) == MSR_SYSCALL_MASK); in guest_msr_calls()
311 GUEST_ASSERT(rdmsr(MSR_GS_BASE) == MSR_GS_BASE); in guest_msr_calls()
313 GUEST_ASSERT(rdmsr(MSR_SYSCALL_MASK) != MSR_SYSCALL_MASK); in guest_msr_calls()
314 GUEST_ASSERT(rdmsr(MSR_GS_BASE) != MSR_GS_BASE); in guest_msr_calls()
321 rdmsr(MSR_IA32_POWER_CTL); in guest_msr_calls()
324 GUEST_ASSERT(rdmsr(0xdeadbeef) == 0xdeadbeef); in guest_msr_calls()
/linux/arch/x86/kernel/
A Dtsc_msr.c181 rdmsr(MSR_PLATFORM_INFO, lo, hi); in cpu_khz_from_msr()
184 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in cpu_khz_from_msr()
189 rdmsr(MSR_FSB_FREQ, lo, hi); in cpu_khz_from_msr()
/linux/arch/x86/kernel/cpu/
A Dcentaur.c32 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
40 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
54 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
184 rdmsr(MSR_IDT_FCR1, lo, hi); in init_centaur()
A Dzhaoxin.c30 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
39 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
/linux/tools/testing/selftests/kvm/include/x86_64/
A Dapic.h68 return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP; in get_bsp_flag()
83 return rdmsr(APIC_BASE_MSR + (reg >> 4)); in x2apic_read_reg()
/linux/tools/power/cpupower/debug/i386/
A Dcentrino-decode.c28 static int rdmsr(unsigned int cpu, unsigned int msr, in rdmsr() function
80 err = rdmsr(cpu, MSR_IA32_PERF_STATUS, &lo, &hi); in decode_live()
/linux/arch/x86/boot/compressed/
A Dmem_encrypt.S43 rdmsr
80 rdmsr
209 rdmsr
A Defi_thunk_64.S124 rdmsr
152 rdmsr
/linux/drivers/ata/
A Dpata_cs5536.c36 #undef rdmsr /* avoid accidental MSR usage on, e.g. x86-64 */
38 #define rdmsr(x, y, z) do { } while (0) macro
91 rdmsr(MSR_IDE_CFG + reg, *val, dummy); in cs5536_read()
A Dpata_cs5535.c113 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); in cs5535_set_piomode()
135 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); in cs5535_set_dmamode()
/linux/arch/x86/mm/
A Dmem_encrypt_boot.S114 rdmsr
147 rdmsr
/linux/drivers/char/hw_random/
A Dvia-rng.c153 rdmsr(MSR_VIA_RNG, lo, hi); in via_rng_init()
177 rdmsr(MSR_VIA_RNG, lo, hi); in via_rng_init()
/linux/drivers/thermal/intel/
A Dtherm_throt.c654 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
680 rdmsr(MSR_THERM2_CTL, l, h); in intel_init_thermal()
691 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); in intel_init_thermal()
705 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); in intel_init_thermal()
722 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
/linux/drivers/misc/
A Dcs5535-mfgpt.c84 rdmsr(msr, value, dummy); in cs5535_mfgpt_toggle_event()
115 rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); in cs5535_mfgpt_set_irq()
129 rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy); in cs5535_mfgpt_set_irq()

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