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Searched refs:readl (Results 1 – 25 of 2202) sorted by relevance

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/linux/drivers/net/ethernet/stmicro/stmmac/
A Dmmc_core.c190 u32 value = readl(mmcaddr + MMC_CNTRL); in dwmac_mmc_ctrl()
292 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS); in dwmac_mmc_read()
294 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS); in dwmac_mmc_read()
298 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS); in dwmac_mmc_read()
329 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR); in dwmac_mmc_read()
332 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK); in dwmac_mmc_read()
344 u32 value = readl(mmcaddr + MMC_CNTRL); in dwxgmac_mmc_ctrl()
362 tmp += readl(addr + reg); in dwxgmac_read_mmc_reg()
363 tmp += ((u64 )readl(addr + reg + 0x4)) << 32; in dwxgmac_read_mmc_reg()
464 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR); in dwxgmac_mmc_read()
[all …]
A Ddwmac4_dma.c19 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
117 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac4_dma_init_channel()
147 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_init()
165 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()
183 readl(ioaddr + DMA_CHAN_CONTROL(channel)); in _dwmac4_dump_dma_regs()
185 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); in _dwmac4_dump_dma_regs()
201 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); in _dwmac4_dump_dma_regs()
215 readl(ioaddr + DMA_CHAN_STATUS(channel)); in _dwmac4_dump_dma_regs()
378 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); in dwmac4_get_hw_feature()
407 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); in dwmac4_get_hw_feature()
[all …]
A Ddwxgmac2_dma.c13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
139 reg_space[i] = readl(ioaddr + i * 4); in dwxgmac2_dma_dump_regs()
285 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
298 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
311 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
380 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0); in dwxgmac2_get_hw_feature()
396 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1); in dwxgmac2_get_hw_feature()
425 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2); in dwxgmac2_get_hw_feature()
437 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3); in dwxgmac2_get_hw_feature()
[all …]
A Dstmmac_hwtstamp.c29 u32 value = readl(ioaddr + PTP_TCR); in config_sub_second_increment()
69 value = readl(ioaddr + PTP_TCR); in init_systime()
86 value = readl(ioaddr + PTP_TCR); in config_addend()
93 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG)) in config_addend()
117 value = readl(ioaddr + PTP_TCR); in adjust_systime()
129 value = readl(ioaddr + PTP_TCR); in adjust_systime()
136 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT)) in adjust_systime()
151 ns = readl(ioaddr + PTP_STNSR); in get_systime()
153 ns += readl(ioaddr + PTP_STSR) * 1000000000ULL; in get_systime()
163 ns = readl(ptpaddr + PTP_ATNR); in get_ptptime()
[all …]
A Ddwmac4_core.c27 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init()
89 value = readl(ioaddr + base_register); in dwmac4_rx_queue_priority()
108 value = readl(ioaddr + base_register); in dwmac4_tx_queue_priority()
131 value = readl(ioaddr + GMAC_RXQ_CTRL1); in dwmac4_rx_queue_routing()
280 reg_space[i] = readl(ioaddr + i * 4); in dwmac4_dump_regs()
295 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_rx_ipc_enable()
427 val = readl(ioaddr + GMAC_VLAN_TAG); in dwmac4_write_single_vlan()
447 val = readl(ioaddr + GMAC_VLAN_TAG); in dwmac4_write_vlan_filter()
456 val = readl(ioaddr + GMAC_VLAN_TAG); in dwmac4_write_vlan_filter()
862 readl(ioaddr + GMAC_PMT); in dwmac4_irq_status()
[all …]
A Ddwmac4_lib.c17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()
45 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
52 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
66 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
91 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()
103 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()
115 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()
209 u32 value = readl(ioaddr + GMAC_CONFIG); in stmmac_dwmac4_set_mac()
225 hi_addr = readl(ioaddr + high); in stmmac_dwmac4_get_mac_addr()
[all …]
A Ddwxgmac2_core.c21 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_core_init()
22 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_core_init()
52 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_set_mac()
53 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_set_mac()
72 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
106 value = readl(ioaddr + reg); in dwxgmac2_rx_queue_prio()
123 value = readl(ioaddr + reg); in dwxgmac2_tx_queue_prio()
208 value = readl(ioaddr + reg); in dwxgmac2_map_mtl_to_dma()
239 reg_space[i] = readl(ioaddr + i * 4); in dwxgmac2_dump_regs()
249 en = readl(ioaddr + XGMAC_INT_EN); in dwxgmac2_host_irq_status()
[all …]
A Ddwmac_lib.c18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
37 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
49 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq()
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
75 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
82 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
236 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
261 u32 value = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
277 hi_addr = readl(ioaddr + high); in stmmac_get_mac_addr()
[all …]
/linux/drivers/media/platform/s5p-jpeg/
A Djpeg-hw-s5p.c45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
60 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
75 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
90 reg = readl(regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
95 reg = readl(regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
137 reg = readl(regs + S5P_JPGY_U); in s5p_jpeg_y()
142 reg = readl(regs + S5P_JPGY_L); in s5p_jpeg_y()
152 reg = readl(regs + S5P_JPGX_U); in s5p_jpeg_x()
157 reg = readl(regs + S5P_JPGX_L); in s5p_jpeg_x()
292 readl(regs + S5P_JPGINTST); in s5p_jpeg_clear_int()
[all …]
A Djpeg-hw-exynos4.c20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
67 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in __exynos4_jpeg_set_img_fmt()
141 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in __exynos4_jpeg_set_enc_out_fmt()
177 reg = readl(base + EXYNOS4_INT_EN_REG) & in exynos4_jpeg_set_interrupt()
185 return readl(base + EXYNOS4_INT_STATUS_REG); in exynos4_jpeg_get_int_status()
190 return readl(base + EXYNOS4_FIFO_STATUS_REG); in exynos4_jpeg_get_fifo_status()
259 reg = readl(base + EXYNOS4_TBL_SEL_REG); in exynos4_jpeg_set_dec_components()
269 reg = readl(base + EXYNOS4_TBL_SEL_REG); in exynos4_jpeg_select_dec_q_tbl()
[all …]
/linux/drivers/scsi/bfa/
A Dbfa_ioc_ct.c134 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
135 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
138 readl(ioc->ioc_regs.err_set); in bfa_ioc_ct_notify_fail()
313 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
343 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
399 readl(ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_ct_ownership_reset()
620 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
631 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
737 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
842 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_nfc_clk_reset()
[all …]
/linux/drivers/phy/mediatek/
A Dphy-mtk-tphy.c376 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
430 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
436 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
501 tmp = readl(com + U3P_USBPHYACR0); in u2_phy_pll_26m_set()
506 tmp = readl(com + U3P_USBPHYACR2); in u2_phy_pll_26m_set()
527 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_init()
532 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_init()
591 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
600 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_power_on()
625 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_reg.c31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
224 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); in analogix_dp_get_pll_lock_status()
242 reg = readl(dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
268 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
277 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
287 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
297 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
307 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
[all …]
/linux/drivers/ata/
A Dahci_xgene.c163 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
165 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
203 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_qc_issue()
274 val = readl(mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
288 val = readl(mmio + PORTPHY5CFG); in xgene_ahci_set_phy_cfg()
292 val = readl(mmio + PORTAXICFG); in xgene_ahci_set_phy_cfg()
298 val = readl(mmio + PORTRANSCFG); in xgene_ahci_set_phy_cfg()
384 val = readl(port_mmio + PORT_SCR_ERR); in xgene_ahci_do_hardreset()
464 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_pmp_softreset()
514 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_softreset()
[all …]
A Dsata_sx4.c707 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
718 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
733 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
746 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
846 tmp = readl(mmio + PDC_CTLSTAT); in pdc_freeze()
879 tmp = readl(mmio); in pdc_reset_port()
891 readl(mmio); /* flush */ in pdc_reset_port()
1001 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_get_from_dimm()
1060 readl(mmio + PDC_GENERAL_CTLR); in pdc20621_put_to_dimm()
1281 readl(mmio + PDC_TIME_CONTROL); in pdc20621_dimm_init()
[all …]
/linux/drivers/net/ethernet/brocade/bna/
A Dbfa_ioc_ct.c194 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
195 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
377 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
400 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
477 readl(ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_ct_ownership_reset()
646 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
661 r32 = readl(rb + PSS_CTL_REG); in bfa_ioc_ct_pll_init()
672 r32 = readl(rb + MBIST_STAT_REG); in bfa_ioc_ct_pll_init()
774 r32 = readl(rb + PSS_CTL_REG); in bfa_ioc_ct2_mem_init()
851 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
A Dsxgbe_core.c26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
122 tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx()
144 return readl(ioaddr + SXGBE_CORE_VERSION_REG); in sxgbe_get_controller_version()
170 reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_enable_rxqueue()
180 reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_disable_rxqueue()
195 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode()
204 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_reset_eee_mode()
213 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_pls()
243 ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx_csum()
[all …]
/linux/drivers/soc/sifive/
A Dsifive_l2_cache.c85 regval = readl(l2_base + SIFIVE_L2_CONFIG); in l2_config_read()
95 regval = readl(l2_base + SIFIVE_L2_WAYENABLE); in l2_config_read()
121 return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; in l2_largest_wayenabled()
156 add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); in l2_int_handler()
157 add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); in l2_int_handler()
160 readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); in l2_int_handler()
166 add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); in l2_int_handler()
168 readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); in l2_int_handler()
175 add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); in l2_int_handler()
178 readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); in l2_int_handler()
[all …]
/linux/drivers/i2c/busses/
A Di2c-pxa.c353 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_show_state()
368 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)), in i2c_pxa_scream_blue_murder()
369 readl(_ISR(i2c))); in i2c_pxa_scream_blue_murder()
427 isr = readl(_ISR(i2c)); in i2c_pxa_wait_bus_not_busy()
453 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_wait_master()
510 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_wait_slave()
811 icr = readl(_ICR(i2c)); in i2c_pxa_stop_message()
998 u32 isr = readl(_ISR(i2c)); in i2c_pxa_handler()
1005 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_handler()
1317 isr = readl(_ISR(i2c)); in i2c_pxa_unprepare_recovery()
[all …]
/linux/drivers/usb/chipidea/
A Dusbmisc_imx.c175 val = readl(usbmisc->base); in usbmisc_imx25_init()
190 val = readl(usbmisc->base); in usbmisc_imx25_init()
227 val = readl(reg); in usbmisc_imx25_post()
323 val = readl(reg) | in usbmisc_imx53_init()
354 val = readl(reg) | in usbmisc_imx53_init()
553 val = readl(reg); in usbmisc_imx6sx_init()
603 val = readl(usbmisc->base); in usbmisc_imx7d_set_wakeup()
628 reg = readl(usbmisc->base); in usbmisc_imx7d_init()
649 reg = readl(usbmisc->base); in usbmisc_imx7d_init()
886 reg = readl(usbmisc->base); in usbmisc_imx7ulp_init()
[all …]
/linux/drivers/media/platform/exynos4-is/
A Dfimc-lite-reg.c25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq()
56 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end()
77 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask()
103 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern()
144 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format()
149 cfg = readl(dev->regs + FLITE_REG_CISRCSIZE); in flite_hw_set_source_format()
163 cfg = readl(dev->regs + FLITE_REG_CIWDOFST); in flite_hw_set_window_offset()
252 cfg = readl(dev->regs + FLITE_REG_CIOCAN); in flite_hw_set_dma_window()
[all …]
/linux/drivers/usb/early/
A Dehci-dbgp.c203 pids = readl(&ehci_debug->pids); in dbgp_wait_until_done()
257 lo = readl(&ehci_debug->data03); in dbgp_get_data()
258 hi = readl(&ehci_debug->data47); in dbgp_get_data()
277 pids = readl(&ehci_debug->pids); in dbgp_bulk_write()
280 ctrl = readl(&ehci_debug->control); in dbgp_bulk_write()
304 pids = readl(&ehci_debug->pids); in dbgp_bulk_read()
307 ctrl = readl(&ehci_debug->control); in dbgp_bulk_read()
440 cmd = readl(&ehci_regs->command); in dbgp_ehci_startup()
471 cmd = readl(&ehci_regs->command); in dbgp_ehci_controller_reset()
475 cmd = readl(&ehci_regs->command); in dbgp_ehci_controller_reset()
[all …]
/linux/drivers/rtc/
A Drtc-ftrtc010.c71 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_read_time()
72 min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE); in ftrtc010_rtc_read_time()
73 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_read_time()
74 days = readl(rtc->rtc_base + FTRTC010_RTC_DAYS); in ftrtc010_rtc_read_time()
92 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_set_time()
93 min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE); in ftrtc010_rtc_set_time()
94 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_set_time()
95 day = readl(rtc->rtc_base + FTRTC010_RTC_DAYS); in ftrtc010_rtc_set_time()
165 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_probe()
167 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_probe()
[all …]
/linux/drivers/mtd/spi-nor/controllers/
A Dintel-spi.c182 i, readl(ispi->base + FDATA(i))); in intel_spi_dump_regs()
188 readl(ispi->base + FREG(i))); in intel_spi_dump_regs()
191 readl(ispi->pregs + PR(i))); in intel_spi_dump_regs()
197 readl(ispi->sregs + PREOP_OPTYPE)); in intel_spi_dump_regs()
199 readl(ispi->sregs + OPMENU0)); in intel_spi_dump_regs()
201 readl(ispi->sregs + OPMENU1)); in intel_spi_dump_regs()
214 value = readl(ispi->pregs + PR(i)); in intel_spi_dump_regs()
322 val = readl(ispi->base + BYT_BCR); in intel_spi_init()
326 val = readl(ispi->base + BYT_BCR); in intel_spi_init()
374 lvscc = readl(ispi->base + LVSCC); in intel_spi_init()
[all …]
/linux/sound/soc/sunxi/
A Dsun8i-adda-pr-regmap.c35 writel(readl(base) | ADDA_PR_RESET, base); in adda_reg_read()
38 writel(readl(base) & ~ADDA_PR_WRITE, base); in adda_reg_read()
41 tmp = readl(base); in adda_reg_read()
47 *val = readl(base) & ADDA_PR_DATA_OUT_MASK; in adda_reg_read()
58 writel(readl(base) | ADDA_PR_RESET, base); in adda_reg_write()
61 tmp = readl(base); in adda_reg_write()
67 tmp = readl(base); in adda_reg_write()
73 writel(readl(base) | ADDA_PR_WRITE, base); in adda_reg_write()
76 writel(readl(base) & ~ADDA_PR_WRITE, base); in adda_reg_write()

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