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Searched refs:reg32 (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/pci/pcie/
A Daer.c140 u32 reg32; in enable_ecrc_checking() local
146 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking()
147 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking()
148 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking()
149 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking()
164 u32 reg32; in disable_ecrc_checking() local
1261 u32 reg32; in aer_enable_rootport() local
1287 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; in aer_enable_rootport()
1301 u32 reg32; in aer_disable_rootport() local
1311 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; in aer_disable_rootport()
[all …]
A Daspm.c172 u32 reg32; in pcie_clkpm_cap_init() local
179 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32); in pcie_clkpm_cap_init()
180 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init()
663 u32 reg32, encoding; in pcie_aspm_cap_init() local
671 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_cap_init()
673 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; in pcie_aspm_cap_init()
676 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; in pcie_aspm_cap_init()
811 u32 reg32; in pcie_aspm_sanity_check() local
834 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_sanity_check()
835 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { in pcie_aspm_sanity_check()
A Dportdrv_core.c67 u32 reg32; in pcie_message_numbers() local
72 &reg32); in pcie_message_numbers()
73 *aer = (reg32 & PCI_ERR_ROOT_AER_IRQ) >> 27; in pcie_message_numbers()
/linux/drivers/pci/
A Dpci-acpi.c287 u32 reg32; in program_hpx_type2() local
338 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; in program_hpx_type2()
343 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; in program_hpx_type2()
348 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; in program_hpx_type2()
352 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32); in program_hpx_type2()
353 reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or; in program_hpx_type2()
356 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) in program_hpx_type2()
357 reg32 &= ~PCI_ERR_CAP_ECRC_GENE; in program_hpx_type2()
358 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC)) in program_hpx_type2()
359 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE; in program_hpx_type2()
[all …]
A Dprobe.c1573 u32 reg32; in set_pcie_hotplug_bridge() local
1575 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32); in set_pcie_hotplug_bridge()
1576 if (reg32 & PCI_EXP_SLTCAP_HPC) in set_pcie_hotplug_bridge()
/linux/drivers/infiniband/hw/hfi1/
A Daspm.c49 u32 reg32; in aspm_hw_set_l1_ent_latency() local
51 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, &reg32); in aspm_hw_set_l1_ent_latency()
52 reg32 &= ~PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK; in aspm_hw_set_l1_ent_latency()
53 reg32 |= l1_ent_lat << PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT; in aspm_hw_set_l1_ent_latency()
54 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
A Dpcie.c947 u32 reg32, fs, lf; in do_pcie_gen3_transition() local
1069 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; in do_pcie_gen3_transition()
1070 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1079 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; in do_pcie_gen3_transition()
1080 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1338 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, &reg32); in do_pcie_gen3_transition()
1345 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
/linux/drivers/net/wireless/ath/ath9k/
A Dar9002_phy.c69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
149 reg32 = reg32 | in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
A Dar5008_phy.c111 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument
118 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer()
209 u32 reg32 = 0; in ar5008_hw_set_channel() local
264 reg32 = in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
A Dar9003_phy.c152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local
205 reg32 = (bMode << 29); in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
213 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
219 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
A Deeprom_4k.c296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local
360 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_4k_power_cal_table()
361 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
366 reg32); in ath9k_hw_set_4k_power_cal_table()
A Deeprom_def.c778 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local
895 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_def_power_cal_table()
896 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
901 reg32); in ath9k_hw_set_def_power_cal_table()
A Deeprom_9287.c365 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local
480 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_ar9287_power_cal_table()
482 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
/linux/drivers/ipack/carriers/
A Dtpci200.c522 u32 reg32; in tpci200_pci_probe() local
556 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
557 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
558 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
560 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
561 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
562 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
/linux/drivers/gpu/drm/bridge/cadence/
A Dcdns-mhdp8546-core.c861 u32 reg32; in cdns_mhdp_link_training_init() local
870 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_init()
1032 u32 reg32; in cdns_mhdp_link_training_channel_eq() local
1042 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_channel_eq()
1249 u32 reg32; in cdns_mhdp_link_training() local
1314 reg32 &= ~GENMASK(1, 0); in cdns_mhdp_link_training()
1315 reg32 |= CDNS_DP_NUM_LANES(mhdp->link.num_lanes); in cdns_mhdp_link_training()
1316 reg32 |= CDNS_DP_WR_FAILING_EDGE_VSYNC; in cdns_mhdp_link_training()
1317 reg32 |= CDNS_DP_FRAMER_EN; in cdns_mhdp_link_training()
1323 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
A Dfw_reset.c240 u32 reg32; in mlx5_pci_link_toggle() local
279 err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, &reg32); in mlx5_pci_link_toggle()
282 if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) { in mlx5_pci_link_toggle()
283 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32); in mlx5_pci_link_toggle()
/linux/drivers/net/ethernet/freescale/fman/
A Dfman_memac.c1035 u32 reg32 = 0; in memac_init() local
1078 reg32 = ioread32be(&memac->regs->command_config); in memac_init()
1079 reg32 &= ~CMD_CFG_CRC_FWD; in memac_init()
1080 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
/linux/kernel/debug/kdb/
A Dkdb_main.c1835 u32 reg32; in kdb_rd() local
1866 rname = dbg_get_reg(i, &reg32, kdb_current_regs); in kdb_rd()
1869 len += kdb_printf("%s: %08x", rname, reg32); in kdb_rd()
1904 u32 reg32; in kdb_rm() local
1943 reg32 = reg64; in kdb_rm()
1944 dbg_set_reg(i, &reg32, kdb_current_regs); in kdb_rm()
/linux/drivers/net/wireless/realtek/rtl818x/rtl8180/
A Ddev.c816 u32 reg32; in rtl8180_init_hw() local
967 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA); in rtl8180_init_hw()
968 reg32 &= 0x00ffff00; in rtl8180_init_hw()
969 reg32 |= 0xb8000054; in rtl8180_init_hw()
970 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32); in rtl8180_init_hw()
/linux/Documentation/translations/zh_TW/filesystems/
A Ddebugfs.rst166 「base」參數可能爲0，但您可能需要使用__stringify構建reg32數組，實際上有許多寄存器
/linux/Documentation/translations/zh_CN/filesystems/
A Ddebugfs.rst164 “base”参数可能为0，但您可能需要使用__stringify构建reg32数组，实际上有许多寄存器
/linux/drivers/net/wireless/realtek/rtl818x/rtl8187/
A Ddev.c1533 u32 reg32; in rtl8187_probe() local
1534 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); in rtl8187_probe()
1535 reg32 &= RTL818X_TX_CONF_HWVER_MASK; in rtl8187_probe()
1536 switch (reg32) { in rtl8187_probe()
/linux/Documentation/filesystems/
A Ddebugfs.rst182 The "base" argument may be 0, but you may want to build the reg32 array
/linux/drivers/net/ethernet/broadcom/
A Dtg3.c2545 u32 reg32, phy9_orig; in tg3_phy_reset_5703_4_5() local
2559 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) in tg3_phy_reset_5703_4_5()
2562 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5()
2563 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2601 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32); in tg3_phy_reset_5703_4_5()
2605 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5()
2606 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()

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