Home
last modified time | relevance | path

Searched refs:reg_base (Results 1 – 25 of 351) sorted by relevance

12345678910>>...15

/linux/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_reg.c242 reg = readl(dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
247 writel(reg, dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
268 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
273 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
277 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
283 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
287 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
293 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
297 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
303 writel(reg, dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
[all …]
/linux/drivers/gpio/
A Dgpio-bcm-kona.c142 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set()
169 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get()
209 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_input()
233 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_output()
270 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set_debounce()
348 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_ack()
369 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_mask()
391 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_unmask()
412 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_set_type()
462 reg_base = bank->kona_gpio->reg_base; in bcm_kona_gpio_irq_handler()
[all …]
A Dgpio-amdpt.c27 void __iomem *reg_base; member
40 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
63 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
65 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
88 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
90 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
94 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
95 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
96 pt_gpio->reg_base + PT_DIRECTION_REG, NULL, in pt_gpio_probe()
119 writel(0, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_probe()
[all …]
A Dgpio-menz127.c34 void __iomem *reg_base; member
69 db_en = readl(priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
79 writel(db_en, priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
95 od_en = readl(priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
103 writel(od_en, priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
150 if (men_z127_gpio->reg_base == NULL) { in men_z127_probe()
158 men_z127_gpio->reg_base + MEN_Z127_PSR, in men_z127_probe()
159 men_z127_gpio->reg_base + MEN_Z127_CTRL, in men_z127_probe()
161 men_z127_gpio->reg_base + MEN_Z127_GPIODR, in men_z127_probe()
179 iounmap(men_z127_gpio->reg_base); in men_z127_probe()
[all …]
/linux/arch/sh/drivers/pci/
A Dpci-sh7780.c100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
229 tmp = __raw_readl(hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
255 chan->reg_base = 0xfe040000; in sh7780_pci_init()
262 chan->reg_base + SH4_PCICR); in sh7780_pci_init()
297 chan->reg_base + SH4_PCICR); in sh7780_pci_init()
309 chan->reg_base + SH4_PCILSR1); in sh7780_pci_init()
325 chan->reg_base + SH4_PCILSR0); in sh7780_pci_init()
[all …]
/linux/drivers/irqchip/
A Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
66 gc->reg_base = reg_base; in ck_set_gc()
111 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
112 if (!reg_base) { in ck_intc_init_comm()
153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
240 writel(0, reg_base + CK_INTC_NEN31_00); in ck_intc_init()
241 writel(0, reg_base + CK_INTC_NEN63_32); in ck_intc_init()
[all …]
A Dirq-digicolor.c57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
63 gc->reg_base = reg_base; in digicolor_set_gc()
74 void __iomem *reg_base; in digicolor_of_init() local
79 reg_base = of_iomap(node, 0); in digicolor_of_init()
80 if (!reg_base) { in digicolor_of_init()
86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
/linux/drivers/net/ethernet/cavium/thunder/
A Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
127 cfg = readq_relaxed(xcv->reg_base + XCV_CTL); in xcv_setup_link()
130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); in xcv_setup_link()
149 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_setup_link()
[all …]
/linux/drivers/ata/
A Dahci_qoriq.c63 struct ccsr_ahci *reg_base; member
173 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
182 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
183 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
184 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
185 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
189 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
200 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
201 writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
209 writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
[all …]
A Dahci_sunxi.c92 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init()
95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()
102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()
103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init()
110 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init()
125 sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); in ahci_sunxi_phy_init()
[all …]
/linux/drivers/remoteproc/
A Dqcom_q6v5_wcss.c110 void __iomem *reg_base; member
161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
344 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
346 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
420 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
422 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
544 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown()
[all …]
/linux/drivers/video/fbdev/mmp/hw/
A Dmmp_spi.c34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local
55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
74 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
83 void __iomem *reg_base = (void __iomem *) in lcd_spi_setup() local
91 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_setup()
102 reg_base + SPU_IOPAD_CONTROL); in lcd_spi_setup()
[all …]
/linux/drivers/net/can/
A Dkvaser_pciefd.c259 void __iomem *reg_base; member
272 void __iomem *reg_base; member
800 iowrite32_rep(can->reg_base + in kvaser_pciefd_start_xmit()
808 __raw_writel(0, can->reg_base + in kvaser_pciefd_start_xmit()
942 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE + in kvaser_pciefd_setup_can_ctrls()
1434 u8 count = ioread32(can->reg_base + in kvaser_pciefd_handle_status_packet()
1472 u8 count = ioread32(can->reg_base + in kvaser_pciefd_handle_eack_packet()
1547 u8 count = ioread32(can->reg_base + in kvaser_pciefd_handle_ack_packet()
1808 if (!pcie->reg_base) { in kvaser_pciefd_probe()
1867 pci_iounmap(pdev, pcie->reg_base); in kvaser_pciefd_probe()
[all …]
/linux/drivers/rtc/
A Drtc-zynqmp.c46 void __iomem *reg_base; member
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
173 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); in xlnx_init_rtc()
175 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); in xlnx_init_rtc()
200 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_interrupt()
233 if (IS_ERR(xrtcdev->reg_base)) in xlnx_rtc_probe()
[all …]
/linux/drivers/spi/
A Dspi-fsl-spi.c93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
293 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
311 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
316 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
460 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
501 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq() local
536 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq() local
556 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control() local
574 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe() local
[all …]
A Dspi-cadence-quadspi.c482 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local
509 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext() local
532 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr() local
564 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read() local
638 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write() local
707 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup() local
739 reg = readl(reg_base + CQSPI_REG_SIZE); in cqspi_read_setup()
742 writel(reg, reg_base + CQSPI_REG_SIZE); in cqspi_read_setup()
752 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute() local
844 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma() local
[all …]
/linux/drivers/clk/samsung/
A Dclk-s5pv210-audss.c24 static void __iomem *reg_base; variable
73 if (IS_ERR(reg_base)) in s5pv210_audss_clk_probe()
74 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
116 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
138 reg_base + ASS_CLK_GATE, 6, 0, &lock); in s5pv210_audss_clk_probe()
144 reg_base + ASS_CLK_GATE, 5, 0, &lock); in s5pv210_audss_clk_probe()
147 reg_base + ASS_CLK_GATE, 4, 0, &lock); in s5pv210_audss_clk_probe()
150 reg_base + ASS_CLK_GATE, 3, 0, &lock); in s5pv210_audss_clk_probe()
153 reg_base + ASS_CLK_GATE, 2, 0, &lock); in s5pv210_audss_clk_probe()
156 reg_base + ASS_CLK_GATE, 1, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
A Dclk-exynos-audss.c22 static void __iomem *reg_base; variable
140 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
141 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
187 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
198 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
214 reg_base + ASS_CLK_GATE, 0, 0, &lock); in exynos_audss_clk_probe()
218 reg_base + ASS_CLK_GATE, 2, 0, &lock); in exynos_audss_clk_probe()
222 reg_base + ASS_CLK_GATE, 3, 0, &lock); in exynos_audss_clk_probe()
226 reg_base + ASS_CLK_GATE, 4, 0, &lock); in exynos_audss_clk_probe()
233 reg_base + ASS_CLK_GATE, 5, 0, &lock); in exynos_audss_clk_probe()
[all …]
/linux/drivers/input/serio/
A Dsun4i-ps2.c85 void __iomem *reg_base; member
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
154 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
161 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
175 writel(rval, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_open()
187 rval = readl(drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_close()
234 if (!drvdata->reg_base) { in sun4i_ps2_probe()
263 writel(0, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_probe()
293 iounmap(drvdata->reg_base); in sun4i_ps2_probe()
[all …]
/linux/drivers/crypto/marvell/octeontx2/
A Dotx2_cptpf_main.c21 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
23 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
28 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
35 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
47 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
49 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
52 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
74 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vf_flr_me_intrs()
80 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vf_flr_me_intrs()
159 otx2_cpt_write64(pf->reg_base, BLKADDR_RVUM, 0, in cptpf_flr_wq_handler()
[all …]
/linux/arch/arm/mach-rockchip/
A Drockchip.c29 void __iomem *reg_base; in rockchip_timer_init() local
36 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
37 if (reg_base) { in rockchip_timer_init()
38 writel(0, reg_base + 0x30); in rockchip_timer_init()
39 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
40 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
41 writel(1, reg_base + 0x30); in rockchip_timer_init()
43 iounmap(reg_base); in rockchip_timer_init()
/linux/arch/powerpc/boot/
A Dns16550.c31 static unsigned char *reg_base; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
43 out_8(reg_base, c); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
49 return in_8(reg_base); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
62 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) { in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
/linux/arch/sparc/kernel/
A Dsbus.c223 imap += reg_base; in sbus_build_irq()
238 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
241 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
244 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
248 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
280 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
281 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
354 afsr_reg = reg_base + SYSIO_CE_AFSR; in sysio_ce_handler()
355 afar_reg = reg_base + SYSIO_CE_AFAR; in sysio_ce_handler()
532 reg_base + ECC_CONTROL); in sysio_register_error_handlers()
[all …]
/linux/drivers/fpga/
A Daltera-pr-ip-core.c29 void __iomem *reg_base; member
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write()
123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write()
126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write()
129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write()
176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument
186 priv->reg_base = reg_base; in alt_pr_register()
[all …]
/linux/drivers/input/keyboard/
A Dnspire-keypad.c32 void __iomem *reg_base; member
91 writel(0x3, keypad->reg_base + KEYPAD_INT); in nspire_keypad_irq()
121 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); in nspire_keypad_open()
124 writel(val, keypad->reg_base + KEYPAD_CNTL); in nspire_keypad_open()
138 writel(0, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_close()
140 writel(~0, keypad->reg_base + KEYPAD_INT); in nspire_keypad_close()
191 if (IS_ERR(keypad->reg_base)) in nspire_keypad_probe()
192 return PTR_ERR(keypad->reg_base); in nspire_keypad_probe()
207 writel(0, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_probe()
209 writel(~0, keypad->reg_base + KEYPAD_INT); in nspire_keypad_probe()
[all …]

Completed in 67 milliseconds

12345678910>>...15