| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_reg.h | 37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
62 REG_SET_N(reg_name, 1, initial_val, \
63 FN(reg_name, field), val)
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
89 REG_UPDATE_N(reg_name, 1, \
90 FN(reg_name, field), val)
112 #define REG_GET(reg_name, field, val) \ argument
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | reg_helper.h | 56 REG(reg_name), \
61 FD(reg_name##__##field)
163 FN(reg_name, f2), v2)
169 FN(reg_name, f3), v3)
176 FN(reg_name, f4), v4)
184 FN(reg_name, f5), v5)
193 FN(reg_name, f6), v6)
203 FN(reg_name, f7), v7)
214 FN(reg_name, f8), v8)
220 REG(reg_name), FN(reg_name, field), val,\
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_services.h | 95 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
98 reg_name ## __ ## reg_field ## _MASK,\
99 reg_name ## __ ## reg_field ## __SHIFT)
111 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
115 reg_name ## __ ## reg_field ## _MASK,\
116 reg_name ## __ ## reg_field ## __SHIFT)
157 …generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name +…
160 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
161 …generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + ins…
167 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| A D | hw_factory_dcn21.c | 57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 #define REGI(reg_name, block, id)\ argument
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
100 .field_name = reg_name ## __ ## field_name ## post_fix
139 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| A D | hw_factory_dce120.c | 46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| A D | hw_factory_dcn20.c | 59 #define REG(reg_name)\ argument
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
103 .field_name = reg_name ## __ ## field_name ## post_fix
156 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| A D | hw_factory_dcn30.c | 67 #define REG(reg_name)\ argument
68 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
70 #define SF_HPD(reg_name, field_name, post_fix)\ argument
73 #define REGI(reg_name, block, id)\ argument
75 mm ## block ## id ## _ ## reg_name
77 #define SF(reg_name, field_name, post_fix)\ argument
78 .field_name = reg_name ## __ ## field_name ## post_fix
110 #define SF_DDC(reg_name, field_name, post_fix)\ argument
111 .field_name = reg_name ## __ ## field_name ## post_fix
164 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| A D | hw_factory_dcn10.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/crypto/ux500/cryp/ |
| A D | cryp_p.h | 23 #define CRYP_SET_BITS(reg_name, mask) \ argument
24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
26 #define CRYP_WRITE_BIT(reg_name, val, mask) \ argument
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
28 ((val) & (mask))), reg_name)
30 #define CRYP_TEST_BITS(reg_name, val) \ argument
31 (readl_relaxed(reg_name) & (val))
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_panel_cntl.h | 32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| A D | hw_factory_dce110.c | 42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
80 .field_name = reg_name ## __ ## field_name ## post_fix
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 114 #define SR(reg_name)\ argument
115 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
116 mm ## reg_name
119 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
124 mm ## reg_name
131 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
152 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
163 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
174 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dwb.h | 36 #define SR(reg_name)\ argument
37 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
38 mm ## reg_name
40 #define SRI(reg_name, block, id)\ argument
41 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
42 mm ## block ## id ## _ ## reg_name
45 #define SRII(reg_name, block, id)\ argument
46 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## id ## _ ## reg_name
49 #define SF(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_resource.c | 251 #define SR(reg_name)\ argument
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
268 .reg_name = ix ## block ## id ## _ ## reg_name
275 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
286 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
287 mm ## reg_name
297 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dwb.h | 37 #define SR(reg_name)\ argument
38 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
39 mm ## reg_name
41 #define SRI(reg_name, block, id)\ argument
42 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
43 mm ## block ## id ## _ ## reg_name
45 #define SRI2(reg_name, block, id)\ argument
46 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
47 mm ## reg_name
49 #define SRII(reg_name, block, id)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| A D | rv1_clk_mgr_clk.c | 43 #define CLK_REG(reg_name, block, inst)\ argument
44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## _ ## inst ## _ ## reg_name
47 #define REG(reg_name) \ argument
48 CLK_REG(reg_name, CLK0, 0)
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| A D | rv1_clk_mgr_vbios_smu.c | 63 #define REG(reg_name) \ argument
64 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
66 #define FN(reg_name, field) \ argument
67 FD(reg_name##__##field)
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 304 #define NBIO_SR(reg_name)\ argument
305 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
306 mm ## reg_name
314 #define SR(reg_name)\ argument
315 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
321 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
324 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
327 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
331 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
335 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 281 #define NBIO_SR(reg_name)\ argument
282 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
283 mm ## reg_name
291 #define SR(reg_name)\ argument
292 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
298 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
301 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
304 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
308 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
312 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
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| /linux/drivers/media/i2c/ccs/ |
| A D | ccs-reg-access.h | 36 #define ccs_read(sensor, reg_name, val) \ argument
37 ccs_read_addr(sensor, CCS_R_##reg_name, val)
39 #define ccs_write(sensor, reg_name, val) \ argument
40 ccs_write_addr(sensor, CCS_R_##reg_name, val)
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| /linux/drivers/crypto/ux500/hash/ |
| A D | hash_alg.h | 98 #define HASH_SET_BITS(reg_name, mask) \ argument
99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
101 #define HASH_CLEAR_BITS(reg_name, mask) \ argument
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| A D | dce112_clk_mgr.c | 37 #define SR(reg_name)\ argument
38 .reg_name = mm ## reg_name
41 #define SRI(reg_name, block, id)\ argument
42 .reg_name = mm ## block ## id ## _ ## reg_name
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr_internal.h | 84 #define CLK_SRI(reg_name, block, inst)\ argument
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
86 mm ## block ## _ ## inst ## _ ## reg_name
119 #define CLK_SF(reg_name, field_name, post_fix)\ argument
120 .field_name = reg_name ## __ ## field_name ## post_fix
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr_vbios_smu.c | 36 #define REG(reg_name) \ argument
37 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
39 #define FN(reg_name, field) \ argument
40 FD(reg_name##__##field)
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | dcn301_smu.c | 38 #define REG(reg_name) \ argument
39 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
41 #define FN(reg_name, field) \ argument
42 FD(reg_name##__##field)
|