Searched refs:reg_ofs (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/staging/vt6656/ |
| A D | mac.c | 80 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_off() argument
87 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_off()
91 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_on() argument
98 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_on()
102 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) in vnt_mac_write_word() argument
109 return vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, in vnt_mac_write_word()
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| A D | mac.h | 362 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
363 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
364 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
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| /linux/arch/arm/mach-bcm/ |
| A D | platsmp-brcmstb.c | 140 const int reg_ofs = cpu_logical_map(cpu) * 8; in cpu_set_boot_addr() local
141 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs); in cpu_set_boot_addr()
142 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs); in cpu_set_boot_addr()
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| /linux/drivers/gpu/drm/imx/dcss/ |
| A D | dcss-ctxld.c | 341 u32 reg_ofs) in dcss_ctxld_write_irqsafe() argument
357 ctx[ctx_id][item_idx].ofs = reg_ofs; in dcss_ctxld_write_irqsafe()
362 u32 val, u32 reg_ofs) in dcss_ctxld_write() argument
365 dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs); in dcss_ctxld_write()
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| A D | dcss-dev.h | 118 u32 reg_ofs);
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| /linux/drivers/clk/ |
| A D | clk-cdce925.c | 227 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare() local
233 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_prepare()
262 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); in cdce925_pll_prepare()
265 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); in cdce925_pll_prepare()
274 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare() local
277 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_unprepare()
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| /linux/drivers/gpu/drm/stm/ |
| A D | ltdc.h | 17 u32 reg_ofs; /* register offset for applicable regs */ member
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| A D | ltdc.c | 56 #define REG_OFS (ldev->caps.reg_ofs)
1161 ldev->caps.reg_ofs = REG_OFS_NONE; in ltdc_get_caps()
1177 ldev->caps.reg_ofs = REG_OFS_4; in ltdc_get_caps()
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| /linux/drivers/gpu/drm/exynos/ |
| A D | exynos_drm_dsi.c | 243 const unsigned int *reg_ofs; member
324 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_write()
329 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_read()
453 .reg_ofs = exynos_reg_ofs,
465 .reg_ofs = exynos_reg_ofs,
477 .reg_ofs = exynos_reg_ofs,
487 .reg_ofs = exynos5433_reg_ofs,
498 .reg_ofs = exynos5433_reg_ofs,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt8173.c | 920 u32 reg_ofs; member
927 .reg_ofs = _reg_ofs, \
1016 base + cku->reg_ofs); in mtk_apmixedsys_init()
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