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Searched refs:res_ctx (Results 1 – 25 of 54) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_enc_cfg.c115 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false; in remove_link_enc_assignment()
120 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_idx] = eng_id; in remove_link_enc_assignment()
171 eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i]; in find_first_avail_link_enc()
247 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false; in clear_enc_assignments()
248 eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].eng_id; in clear_enc_assignments()
267 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i] = ENGINE_ID_UNKNOWN; in link_enc_cfg_init()
272 state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; in link_enc_cfg_init()
378 dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i] = in link_enc_cfg_link_encs_assign()
379 state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in link_enc_cfg_link_encs_assign()
383 state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; in link_enc_cfg_link_encs_assign()
[all …]
A Ddc_resource.c1321 struct resource_context *res_ctx = &context->res_ctx; in acquire_free_pipe_for_head() local
1875 &new_ctx->res_ctx, in dc_remove_stream_from_ctx()
1894 &new_ctx->res_ctx, in dc_remove_stream_from_ctx()
2110 &context->res_ctx, in resource_map_pool_resources()
2140 &context->res_ctx, pool, in resource_map_pool_resources()
2162 &context->res_ctx, pool, in resource_map_pool_resources()
2291 &new_ctx->res_ctx, in dc_validate_global_state()
2297 &new_ctx->res_ctx, in dc_validate_global_state()
2783 &context->res_ctx, in resource_map_clock_resources()
2789 &context->res_ctx, in resource_map_clock_resources()
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A Ddc_stream.c259 struct resource_context *res_ctx; in program_cursor_attributes() local
265 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
359 struct resource_context *res_ctx; in program_cursor_position() local
365 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
563 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
564 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
569 if (res_ctx->pipe_ctx[i].stream != stream) in dc_stream_get_vblank_counter()
584 struct resource_context *res_ctx; in dc_stream_send_dp_sdp() local
592 res_ctx = &dc->current_state->res_ctx; in dc_stream_send_dp_sdp()
622 struct resource_context *res_ctx = in dc_stream_get_scanoutpos() local
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A Ddc.c1089 context->res_ctx.pipe_ctx[i].top_pipe != dc->current_state->res_ctx.pipe_ctx[i].top_pipe; in disable_dangling_plane()
1136 pipe = &context->res_ctx.pipe_ctx[i]; in disable_vbios_mode_if_required()
1326 …if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event… in enable_timing_multisync()
1349 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe) in program_timing_sync()
1630 pipe = &context->res_ctx.pipe_ctx[i]; in dc_enable_stereo()
1727 pipe = &context->res_ctx.pipe_ctx[i]; in dc_commit_state_no_check()
1766 pipe = &context->res_ctx.pipe_ctx[k]; in dc_commit_state_no_check()
1849 struct resource_context *res_ctx = &dc->current_state->res_ctx; in dc_acquire_release_mpc_3dlut() local
1852 if (pool && res_ctx) { in dc_acquire_release_mpc_3dlut()
1881 pipe = &context->res_ctx.pipe_ctx[i]; in is_flip_pending_in_pipes()
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A Ddc_link_hwss.c83 link->dc->current_state->res_ctx.pipe_ctx; in dp_enable_link_phy()
434 &link->dc->current_state->res_ctx.pipe_ctx[0]; in dp_retrain_link_dp_test()
896 if (state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc &&
897 state->res_ctx.pipe_ctx[i].stream &&
898 state->res_ctx.pipe_ctx[i].stream->link == link &&
899 !state->res_ctx.pipe_ctx[i].stream->dpms_off) {
900 setup_dp_hpo_stream(&state->res_ctx.pipe_ctx[i], false);
A Ddc_debug.c309 struct resource_context *res_ctx) in context_timing_trace() argument
319 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace()
331 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace()
A Ddc_surface.c152 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
164 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dresource.h115 struct resource_context *res_ctx,
120 struct resource_context *res_ctx,
125 struct resource_context *res_ctx,
138 struct resource_context *res_ctx,
142 struct resource_context *res_ctx,
146 struct resource_context *res_ctx,
157 struct resource_context *res_ctx,
190 struct resource_context *res_ctx,
A Dcore_types.h167 struct resource_context *res_ctx,
172 struct resource_context *res_ctx,
185 struct resource_context *res_ctx,
192 struct resource_context *res_ctx,
474 struct resource_context res_ctx; member
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c1778 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { in remove_dsc_from_stream_resource()
1887 struct resource_context *res_ctx, in dcn20_split_stream_for_odm() argument
1970 struct resource_context *res_ctx, in dcn20_split_stream_for_mpc() argument
2008 struct resource_context *res_ctx = &context->res_ctx; in dcn20_populate_dml_pipes_from_context() local
2011 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_pipes_from_context()
2019 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_pipes_from_context()
2106 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
2268 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) in dcn20_populate_dml_pipes_from_context()
2880 dc, &context->res_ctx, in dcn20_fast_validate_bw()
2909 dc, &context->res_ctx, in dcn20_fast_validate_bw()
[all …]
A Ddcn20_resource.h131 void dcn20_release_dsc(struct resource_context *res_ctx,
136 struct resource_context *res_ctx,
142 struct resource_context *res_ctx,
146 struct resource_context *res_ctx,
150 struct resource_context *res_ctx,
A Ddcn20_hwseq.c1690 &context->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
1694 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable in dcn20_program_front_end_for_ctx()
1695 && !context->res_ctx.pipe_ctx[i].top_pipe in dcn20_program_front_end_for_ctx()
1696 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe in dcn20_program_front_end_for_ctx()
1697 && context->res_ctx.pipe_ctx[i].stream) in dcn20_program_front_end_for_ctx()
1718 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1731 pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1762 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_post_unlock_program_front_end()
1775 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_post_unlock_program_front_end()
2237 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) in dcn20_reset_back_end_for_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.h72 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 struct resource_context *res_ctx,
87 struct resource_context *res_ctx,
A Ddcn30_resource.c1465 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1470 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1607 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1653 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1689 struct resource_context *res_ctx, in dcn30_release_post_bldn_3dlut() argument
1758 struct resource_context *res_ctx, in dcn30_split_stream_for_mpc_or_odm() argument
1836 pipe = &context->res_ctx.pipe_ctx[i]; in dcn30_find_split_pipe()
1851 pipe = &context->res_ctx.pipe_ctx[i]; in dcn30_find_split_pipe()
2032 dc, &context->res_ctx, in dcn30_internal_validate_bw()
2054 dc, &context->res_ctx, in dcn30_internal_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c65 struct resource_context *res_ctx, in dcn20_populate_dml_writeback_from_context() argument
73 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
75 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
A Ddcn20_fpu.h31 struct resource_context *res_ctx,
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_hw_sequencer.c56 struct resource_context *res_ctx = &context->res_ctx; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce60_apply_ctx_for_surface()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddmub_psr.c262 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_psr_copy_settings() local
266 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
267 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
268 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
269 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_hw_sequencer.c1754 &dc->current_state->res_ctx.pipe_ctx[i]);
1935 struct resource_context *res_ctx, argument
1947 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1951 res_ctx->pipe_ctx[i].plane_res.mi,
1960 res_ctx->pipe_ctx[i].plane_res.mi,
2050 struct resource_context *res_ctx = &context->res_ctx; local
2065 if (res_ctx->pipe_ctx[i].stream) {
2067 pipe_ctx = &res_ctx->pipe_ctx[i];
2142 &dc->current_state->res_ctx.pipe_ctx[i];
2324 &dc->current_state->res_ctx.pipe_ctx[i];
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A Ddce110_resource.c945 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in build_mapped_resource()
978 context->res_ctx.pipe_ctx, in dce110_validate_bandwidth()
1128 struct resource_context *res_ctx = &context->res_ctx; in dce110_acquire_underlay() local
1130 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; in dce110_acquire_underlay()
1132 if (res_ctx->pipe_ctx[underlay_idx].stream) in dce110_acquire_underlay()
1144 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { in dce110_acquire_underlay()
1198 struct resource_context *res_ctx, in dce110_find_first_free_match_stream_enc_for_link() argument
1207 if (!res_ctx->is_stream_enc_acquired[i] && in dce110_find_first_free_match_stream_enc_for_link()
A Ddce110_resource.h49 struct resource_context *res_ctx,
/linux/drivers/gpu/drm/amd/display/dc/dce100/
A Ddce100_hw_sequencer.c112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
A Ddce100_resource.h50 struct resource_context *res_ctx,
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_resource.h46 struct resource_context *res_ctx,
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_trace.h28 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \

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