| /linux/drivers/bus/fsl-mc/ |
| A D | fsl-mc-allocator.c | 60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
79 res_pool->free_count++; in fsl_mc_resource_pool_add_device()
80 res_pool->max_count++; in fsl_mc_resource_pool_add_device()
124 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_remove_device()
140 res_pool->free_count--; in fsl_mc_resource_pool_remove_device()
141 res_pool->max_count--; in fsl_mc_resource_pool_remove_device()
212 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_allocate()
217 res_pool->free_count--; in fsl_mc_resource_allocate()
237 res_pool->free_count >= res_pool->max_count) in fsl_mc_resource_free()
244 res_pool->free_count++; in fsl_mc_resource_free()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_hwseq.c | 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
113 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
157 if (res_pool->dccg && res_pool->hubbub) { in dcn31_init_hw()
159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
163 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn31_init_hw()
249 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn31_init_hw()
293 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn31_init_hw()
306 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn31_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_hwseq.c | 225 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
228 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
229 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
251 if (res_pool->dccg && res_pool->hubbub) { in dcn201_init_hw()
252 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
256 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
304 res_pool->mpc->funcs->mpc_init(res_pool->mpc); in dcn201_init_hw()
308 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
341 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()
394 struct mpc *mpc = dc->res_pool->mpc; in dcn201_plane_atomic_disconnect()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_hwseq.c | 235 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
284 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
365 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); in dcn30_disable_writeback()
439 struct resource_pool *res_pool = dc->res_pool; in dcn30_init_hw() local
449 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn30_init_hw()
496 if (res_pool->dccg && res_pool->hubbub) { in dcn30_init_hw()
498 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn30_init_hw()
502 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn30_init_hw()
582 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn30_init_hw()
654 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn30_init_hw()
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| A D | dcn30_resource.c | 1469 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1488 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1605 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1764 const struct resource_pool *pool = dc->res_pool; in dcn30_split_stream_for_mpc_or_odm()
1832 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1849 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1880 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn30_internal_validate_bw()
1951 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2082 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2233 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn30_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_hwseq.c | 1473 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in dcn20_update_dchubp_dpp()
1608 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); in dcn20_program_pipe()
1793 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); in dcn20_post_unlock_program_front_end()
2046 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); in dcn20_init_vm_ctx()
2064 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn20_init_sys_ctx()
2482 struct resource_pool *res_pool = dc->res_pool; in dcn20_fpga_init_hw() local
2490 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn20_fpga_init_hw()
2530 res_pool->mpc->funcs->mpc_init(res_pool->mpc); in dcn20_fpga_init_hw()
2534 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
2569 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn20_fpga_init_hw()
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| A D | dcn20_resource.c | 1612 link->dc->res_pool->funcs->link_encs_assign) { in get_pixel_clock_parameters()
1694 const struct resource_pool *pool = dc->res_pool; in dcn20_acquire_dsc()
1747 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1892 const struct resource_pool *pool = dc->res_pool; in dcn20_split_stream_for_odm()
2429 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
2475 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
2590 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
2682 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
2915 &context->res_ctx, dc->res_pool, in dcn20_fast_validate_bw()
2995 if (dc->res_pool->funcs->populate_dml_pipes) in dcn20_calculate_wm()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer.c | 142 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
838 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn10_bios_golden_init()
1348 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
1374 struct resource_pool *res_pool = dc->res_pool; in dcn10_init_hw() local
1388 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) in dcn10_init_hw()
1389 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn10_init_hw()
1423 if (res_pool->dccg && res_pool->hubbub) { in dcn10_init_hw()
1425 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn10_init_hw()
1429 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn10_init_hw()
1932 dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc, in dcn10_cursor_lock()
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| A D | dcn10_hw_sequencer_debug.c | 80 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
84 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
112 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
190 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
232 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
289 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
329 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
384 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
415 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
490 struct resource_pool *pool = dc->res_pool; in dcn10_clear_otpc_underflow()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_link_hwss.c | 85 link->dc->res_pool->dp_clock_source; in dp_enable_link_phy()
801 dc->res_pool->dccg,
808 dc->res_pool->dccg,
825 dc->res_pool->dccg,
829 dc->res_pool->dccg,
856 dc->res_pool->dccg,
862 dc->res_pool->dccg,
867 dc->res_pool->dccg,
874 dc->res_pool->dccg,
880 dc->res_pool->dccg,
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| A D | dc.c | 990 if (!dc->res_pool) in dc_construct()
997 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
1159 dc->res_pool->stream_enc[j]); in disable_vbios_mode_if_required()
1165 dc->res_pool->dp_clock_source, in disable_vbios_mode_if_required()
1232 dc->res_pool->stream_enc_count); in dc_create()
1240 if (dc->res_pool->dmcu != NULL) in dc_create()
1505 dc->res_pool->stream_enc[i]); in dc_validate_seamless_boot_timing()
1569 dc->res_pool->dp_clock_source, in dc_validate_seamless_boot_timing()
1911 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]); in process_deferred_updates()
3355 dc->res_pool, in dc_submit_i2c()
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| A D | dc_resource.c | 167 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
250 if (res_pool != NULL) { in dc_create_resource_pool()
268 return res_pool; in dc_create_resource_pool()
274 if (dc->res_pool) in dc_destroy_resource_pool()
275 dc->res_pool->funcs->destroy(&dc->res_pool); in dc_destroy_resource_pool()
1876 dc->res_pool, in dc_remove_stream_from_ctx()
1886 &new_ctx->res_ctx, dc->res_pool, in dc_remove_stream_from_ctx()
1895 dc->res_pool, in dc_remove_stream_from_ctx()
1900 dc->res_pool, in dc_remove_stream_from_ctx()
2292 dc->res_pool, in dc_validate_global_state()
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| A D | dc_link_enc_cfg.c | 38 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
39 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
152 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
170 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
234 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in get_link_enc_used_by_link()
263 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_init()
264 if (dc->res_pool->link_encoders[i]) in link_enc_cfg_init()
292 dc->res_pool->funcs->link_enc_unassign(state, streams[i]); in link_enc_cfg_link_encs_assign()
492 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
494 link_enc = dc->res_pool->link_encoders[i]; in link_enc_cfg_get_next_avail_link_enc()
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| A D | dc_stream.c | 206 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) in dc_copy_stream()
456 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
476 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
487 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
709 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { in dc_stream_add_dsc_to_resource()
710 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); in dc_stream_add_dsc_to_resource()
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| A D | dc_link.c | 73 link->dc->res_pool); in add_dp_hpo_link_encoder_to_link()
116 link->dc->res_pool->dig_link_enc_count--; in dc_link_destruct()
502 &link->dc->res_pool->audio_support; in link_detect_sink()
1497 if (link->dc->res_pool->funcs->link_init) in dc_link_construct_legacy()
1624 link->dc->res_pool->dig_link_enc_count++; in dc_link_construct_legacy()
2873 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_get_backlight_level()
2950 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_set_psr_allow_active()
2951 struct dmub_psr *psr = dc->res_pool->psr; in dc_link_set_psr_allow_active()
2994 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_get_psr_state()
3062 dmcu = dc->res_pool->dmcu; in dc_link_setup_psr()
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| A D | dc_debug.c | 314 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in context_timing_trace()
318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_hw_sequencer.c | 1673 dc->res_pool->stream_enc[j]);
2080 if (i == dc->res_pool->pipe_count)
2191 dc->res_pool,
2244 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2247 dc->res_pool->dccg, 0);
2272 if (i == dc->res_pool->pipe_count) {
2651 xfm = dc->res_pool->transforms[i];
2701 abm = dc->res_pool->abm;
2705 dmcu = dc->res_pool->dmcu;
2914 dc->res_pool->transforms[fe_idx]);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_hwseq.c | 83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
168 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
187 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
208 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
237 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
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| A D | dcn21_resource.c | 1113 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1142 if (dc->res_pool->funcs->populate_dml_pipes) in dcn21_calculate_wm()
1143 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, in dcn21_calculate_wm()
1201 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); in dcn21_fast_validate_bw()
1235 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1259 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1269 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); in dcn21_fast_validate_bw()
1288 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); in dcn21_fast_validate_bw()
1302 &context->res_ctx, dc->res_pool, in dcn21_fast_validate_bw()
1592 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); in update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 111 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
145 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
148 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
176 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
178 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
222 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
242 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
243 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
246 hpd_state = dc_get_hpd_state_dcn20(dc->res_pool->irqs, irq_src); in dcn2_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| A D | dce100_hw_sequencer.c | 112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/modules/power/ |
| A D | power_helpers.c | 662 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
673 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) in dmub_init_abm_config()
676 if (res_pool->abm == NULL) in dmub_init_abm_config()
732 if (res_pool->multiple_abms[inst]) { in dmub_init_abm_config()
733 result = res_pool->multiple_abms[inst]->funcs->init_abm_config( in dmub_init_abm_config()
734 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); in dmub_init_abm_config()
737 result = res_pool->abm->funcs->init_abm_config( in dmub_init_abm_config()
738 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); in dmub_init_abm_config()
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| A D | power_helpers.h | 51 bool dmub_init_abm_config(struct resource_pool *res_pool,
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_hw_sequencer.c | 57 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce60_should_enable_fbc()
70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
|