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/linux/Documentation/devicetree/bindings/reset/
A Dzynq-reset.txt25 0 : soft reset
26 32 : ddr reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
31 160: gem0 reset
32 161: gem1 reset
41 224: spi0 reset
42 225: spi1 reset
58 416: smc reset
[all …]
A Dsocionext,uniphier-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
27 - description: Media I/O (MIO) reset, SD reset
55 "#reset-cells":
62 - "#reset-cells"
70 reset {
72 #reset-cells = <1>;
83 reset {
96 reset {
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A Dreset.txt10 reset consumer (the module being reset, or a module managing when a sub-
14 A reset signal is represented by the phandle of the provider, plus a reset
24 may be reset. Instead, reset signals should be represented in the DT node
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
37 reset outputs.
41 rst: reset-controller {
42 #reset-cells = <1>;
55 reset-names: List of reset signal name strings sorted in the same order as
57 match reset signal names with reset specifiers.
63 reset-names = "reset";
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A Dti-syscon-reset.txt27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
35 Cell #2 : bit position of the reset in the reset
39 Cell #4 : bit position of the reset in the reset
44 reset status register
57 to a reset specifier as defined above.
59 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
74 pscrst: reset-controller {
76 #reset-cells = <1>;
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A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
21 Specifying reset lines connected to IP modules:
24 resets = <&reset HSDK_V1_ETH_RESET>;
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A Dsocionext,uniphier-glue-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
34 "#reset-cells":
53 reset-names:
66 - "#reset-cells"
70 - reset-names
80 usb_rst: reset@0 {
83 #reset-cells = <1>;
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A Dxlnx,zynqmp-reset.txt9 Please also refer to reset.txt in this directory for common reset
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
27 zynqmp_reset: reset-controller {
28 compatible = "xlnx,zynqmp-reset";
29 #reset-cells = <1>;
34 Specifying reset lines connected to IP modules
39 specified in reset.txt.
42 <dt-bindings/reset/xlnx-zynqmp-resets.h>
44 <dt-bindings/reset/xlnx-versal-resets.h>
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A Dsnps,axs10x-reset.txt1 Binding for the AXS10x reset controller
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
24 #reset-cells = <1>;
28 Specifying reset lines connected to IP modules:
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A Dimg,pistachio-reset.txt13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
37 Specifying reset control of devices
43 Documentation/devicetree/bindings/reset/reset.txt.
50 reset-names = "rst";
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A Dfsl,imx7-src.yaml4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
13 The system reset controller can be used to reset various set of
16 specified in reset.txt.
18 For list of all valid reset indices see
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
45 '#reset-cells':
52 - '#reset-cells'
60 reset-controller@30390000 {
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A Dbrcm,brcmstb-reset.txt1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
12 - compatible: should be brcm,brcmstb-reset
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
21 #reset-cells = <1>;
25 resets = <&reset 26>;
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A Dallwinner,sun6i-a31-clock-reset.yaml4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
20 - allwinner,sun6i-a31-ahb1-reset
21 - allwinner,sun6i-a31-clock-reset
31 "#reset-cells":
40 - allwinner,sun6i-a31-ahb1-reset
41 - allwinner,sun6i-a31-clock-reset
47 - "#reset-cells"
55 ahb1_rst: reset@1c202c0 {
56 #reset-cells = <1>;
62 apbs_rst: reset@80014b0 {
[all …]
A Dnuvoton,npcm-reset.txt4 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
6 - #reset-cells: must be set to 2
9 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
10 NPCM7xx contain four software reset that represent numbers 1 to 4.
12 If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
16 compatible = "nuvoton,npcm750-reset";
18 #reset-cells = <2>;
19 nuvoton,sw-reset-number = <2>;
22 Specifying reset lines connected to IP NPCM7XX modules
32 The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
A Dhisilicon,hi3660-reset.yaml4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
13 Please also refer to reset.txt in this directory for common reset
22 - const: hisilicon,hi3660-reset
24 - const: hisilicon,hi3670-reset
25 - const: hisilicon,hi3660-reset
28 description: phandle of the reset's syscon.
31 '#reset-cells':
38 Cell #2 : bit position of the reset in the reset control register
58 compatible = "hisilicon,hi3660-reset";
60 #reset-cells = <2>;
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A Dlantiq,reset.txt1 Lantiq XWAY SoC RCU reset controller binding
12 "lantiq,danube-reset"
13 "lantiq,xrx200-reset"
16 - Offset of the reset set register
17 - Offset of the reset status register
19 reset line, should be 2.
20 The first cell takes the reset set bit and the
24 Example for the reset-controllers on the xRX200 SoCs:
25 reset0: reset-controller@10 {
26 compatible = "lantiq,xrx200-reset";
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A Dintel,rcu-gw.yaml4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
22 intel,global-reset:
31 "#reset-cells":
35 First cell is reset request register offset.
37 Third cell is bit offset in reset status register.
39 reset request and reset status registers is same. Whereas
45 - intel,global-reset
46 - "#reset-cells"
52 rcu0: reset-controller@e0000000 {
55 intel,global-reset = <0x10 30>;
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/linux/drivers/reset/
A D.built-in.a.cmd1 …reset/built-in.a := echo >/dev/null; rm -f drivers/reset/built-in.a; /usr/bin/ccache /home/test/wo…
A DMakefile6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
13 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
14 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
16 obj-$(CONFIG_RESET_K210) += reset-k210.o
20 obj-$(CONFIG_RESET_MESON) += reset-meson.o
22 obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
29 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
[all …]
A Dbuilt-in.a6 tegra/reset-bpmp.o/
7 reset-brcmstb.o/
9 reset-imx7.o/
10 reset-meson.o/
11 reset-qcom-aoss.o/
13 reset-scmi.o/
14 reset-simple.o/
15 reset-sunxi.o/
16 reset-ti-sci.o/
17 reset-uniphier.o/
[all …]
A DKconfig30 AR71xx SoC reset controller.
53 tristate "Broadcom STB reset controller"
61 tristate "Broadcom STB RESCAL reset controller"
92 Say Y to control the reset signals provided by reset controller.
118 bool "Microchip Sparx5 reset driver"
182 initialization routines as reset lines.
206 This enables a simple reset controller driver for reset lines that
215 - RCC reset controller in STM32 MCUs
278 source "drivers/reset/sti/Kconfig"
279 source "drivers/reset/hisilicon/Kconfig"
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/linux/Documentation/driver-api/
A Dreset.rst15 over their reset input signals, and the `reset controller driver interface
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
31 Physical reset line carrying a reset signal from a reset controller
40 reset line.
52 reset line.
61 trigger reset pulses, or to query reset line status.
64 reset inputs, which are mapped to an actual reset control on an existing reset
127 Only some reset controllers support querying the current status of a reset
130 reset line is asserted.
159 assert or deassert reset signals, to trigger a reset pulse on a reset line, or
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/linux/drivers/power/reset/
A Dat91-reset.c93 : "r" (reset->ramc_base[0]), in at91_reset()
94 "r" (reset->ramc_base[1]), in at91_reset()
95 "r" (reset->rstc_base), in at91_reset()
98 "r" (reset->args), in at91_reset()
99 "r" (reset->ramc_lpr) in at91_reset()
187 struct at91_reset *reset; in at91_reset_probe() local
191 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in at91_reset_probe()
192 if (!reset) in at91_reset_probe()
217 reset->nb.priority = 192; in at91_reset_probe()
221 if (IS_ERR(reset->sclk)) in at91_reset_probe()
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
A Dkeystone-reset.txt3 This node is intended to allow SoC reset in case of software reset
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
37 Setup keystone reset so that in case software reset or
50 rstctrl: reset-controller {
51 compatible = "ti,keystone-reset";
58 Setup keystone reset so that in case of software reset or
61 rstctrl: reset-controller {
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/linux/drivers/soc/ti/
A Domap_prm.c760 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
768 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
784 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_assert()
786 writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); in omap_reset_assert()
815 writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); in omap_reset_deassert()
823 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_deassert()
825 writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); in omap_reset_deassert()
897 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in omap_prm_reset_init()
898 if (!reset) in omap_prm_reset_init()
929 if ((v & reset->mask) != reset->mask) { in omap_prm_reset_init()
[all …]
/linux/Documentation/devicetree/bindings/pci/
A Dqcom,pcie.txt178 - reset-names:
182 - "axi" AXI reset
183 - "ahb" AHB reset
184 - "por" POR reset
185 - "pci" PCI reset
188 - reset-names:
194 - reset-names:
212 - reset-names:
224 - reset-names:
237 - reset-names:
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