| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_hubp.c | 306 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) in hubp21_validate_dml_output()
308 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); in hubp21_validate_dml_output()
309 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) in hubp21_validate_dml_output()
311 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); in hubp21_validate_dml_output()
312 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) in hubp21_validate_dml_output()
314 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); in hubp21_validate_dml_output()
318 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) in hubp21_validate_dml_output()
320 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); in hubp21_validate_dml_output()
323 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); in hubp21_validate_dml_output()
324 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) in hubp21_validate_dml_output()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_hubp.c | 1344 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) in hubp2_validate_dml_output()
1346 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); in hubp2_validate_dml_output()
1347 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) in hubp2_validate_dml_output()
1349 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); in hubp2_validate_dml_output()
1350 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) in hubp2_validate_dml_output()
1352 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); in hubp2_validate_dml_output()
1356 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) in hubp2_validate_dml_output()
1358 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); in hubp2_validate_dml_output()
1361 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); in hubp2_validate_dml_output()
1362 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) in hubp2_validate_dml_output()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_hubp.c | 82 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp201_program_requestor()
83 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp201_program_requestor()
84 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp201_program_requestor()
85 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp201_program_requestor()
86 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height); in hubp201_program_requestor()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hubp.c | 566 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp1_program_requestor()
567 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp1_program_requestor()
568 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp1_program_requestor()
570 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp1_program_requestor()
571 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp1_program_requestor()
572 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp1_program_requestor()
1080 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp1_read_state()
1081 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp1_read_state()
1082 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, in hubp1_read_state()
1084 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, in hubp1_read_state()
[all …]
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| A D | dcn10_hw_sequencer_debug.c | 213 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_get_rq_states()
214 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_get_rq_states()
215 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_get_rq_states()
216 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_get_rq_states()
217 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_get_rq_states()
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| A D | dcn10_hw_sequencer.c | 210 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_log_hubp_states()
211 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_log_hubp_states()
212 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_log_hubp_states()
213 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_log_hubp_states()
214 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_log_hubp_states()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_hubp.c | 439 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp3_read_state()
440 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp3_read_state()
441 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, in hubp3_read_state()
442 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, in hubp3_read_state()
443 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, in hubp3_read_state()
444 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp3_read_state()
445 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); in hubp3_read_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_rq_dlg_helpers.c | 183 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_l); in print__rq_regs_st()
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| A D | display_mode_structs.h | 532 display_data_rq_regs_st rq_regs_l; member
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| A D | dml1_display_rq_dlg_calc.c | 239 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); in dml1_extract_rq_regs()
243 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); in dml1_extract_rq_regs()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); in extract_rq_regs()
198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); in extract_rq_regs()
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| A D | display_rq_dlg_calc_20v2.c | 196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); in extract_rq_regs()
198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); in extract_rq_regs()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 174 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); in extract_rq_regs()
176 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( in extract_rq_regs()
187 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); in extract_rq_regs()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 121 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); in extract_rq_regs()
123 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), in extract_rq_regs()
132 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); in extract_rq_regs()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 204 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); in extract_rq_regs()
206 …rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height),… in extract_rq_regs()
213 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); in extract_rq_regs()
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