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Searched refs:rt_sysc_r32 (Results 1 – 12 of 12) sorted by relevance

/linux/arch/mips/pci/
A Dpci-rt3883.c308 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
309 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); in rt3883_pci_preinit()
310 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
321 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
325 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
329 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
333 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
383 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
390 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
394 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
A Dpci-mt7620.c243 if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { in mt7620_pci_hw_init()
/linux/arch/mips/ralink/
A Dmt7620.c71 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); in mt7620_get_xtal_rate()
83 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); in mt7620_get_periph_rate()
99 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); in mt7620_get_cpu_pll_rate()
125 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); in mt7620_get_pll_rate()
142 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_cpu_rate()
175 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_sys_rate()
263 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in ralink_clk_init()
A Dreset.c33 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_assert_device()
48 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_deassert_device()
A Drt305x.c61 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()
114 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); in ralink_clk_init()
A Drt288x.c23 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()
A Drt3883.c27 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); in ralink_clk_init()
/linux/arch/mips/include/asm/mach-ralink/
A Dralink_regs.h40 static inline u32 rt_sysc_r32(unsigned reg) in rt_sysc_r32() function
47 u32 val = rt_sysc_r32(reg) & ~clr; in rt_sysc_m32()
A Dmt7620.h96 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; in mt7620_get_eco()
/linux/drivers/watchdog/
A Dmt7621_wdt.c100 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in mt7621_wdt_bootcause()
A Drt2880_wdt.c114 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in rt288x_wdt_bootcause()
/linux/drivers/pinctrl/ralink/
A Dpinctrl-rt2880.c141 mode = rt_sysc_r32(reg); in rt2880_pmx_group_enable()

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