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Searched refs:sandybridge_pcode_write (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/i915/
A Dintel_pcode.h18 #define sandybridge_pcode_write(i915, mbox, val) \ macro
A Dintel_pm.c3742 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, in intel_enable_sagv()
/linux/drivers/gpu/drm/i915/gt/
A Dintel_llc.c143 sandybridge_pcode_write(i915, in gen6_update_ring_freq()
A Dintel_rc6.c274 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); in gen6_rc6_enable()
/linux/drivers/gpu/drm/i915/display/
A Dintel_cdclk.c793 ret = sandybridge_pcode_write(dev_priv, in bdw_set_cdclk()
822 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
1126 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1695 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
A Dintel_hdcp.c300 ret = sandybridge_pcode_write(dev_priv, in intel_hdcp_load_keys()
A Dintel_display_power.c5372 if (sandybridge_pcode_write(dev_priv, in hsw_write_dcomp()
A Dintel_display.c1741 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, in hsw_enable_ips()
1772 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); in hsw_disable_ips()

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