/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
A D | dcn201_dpp.c | 182 struct scaler_data *scl_data, in dpp201_get_optimal_number_of_taps() argument 187 if (scl_data->viewport.width > scl_data->recout.width) in dpp201_get_optimal_number_of_taps() 192 if (scl_data->viewport.width != scl_data->h_active && in dpp201_get_optimal_number_of_taps() 193 scl_data->viewport.height != scl_data->v_active && in dpp201_get_optimal_number_of_taps() 198 if (scl_data->viewport.width > scl_data->h_active && in dpp201_get_optimal_number_of_taps() 214 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps() 216 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps() 222 scl_data->taps.v_taps = 8; in dpp201_get_optimal_number_of_taps() 224 scl_data->taps.v_taps = 4; in dpp201_get_optimal_number_of_taps() 246 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps() [all …]
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A D | dcn201_dpp.h | 72 struct scaler_data scl_data; member
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
A D | dcn10_dpp_dscl.c | 342 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter() 345 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter() 362 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter() 364 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter() 371 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); in dpp1_dscl_set_scl_filter() 373 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); in dpp1_dscl_set_scl_filter() 445 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dpp1_dscl_calc_lb_num_partitions() 446 scl_data->viewport.width : scl_data->recout.width; in dpp1_dscl_calc_lb_num_partitions() 448 scl_data->viewport_c.width : scl_data->recout.width; in dpp1_dscl_calc_lb_num_partitions() 725 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) in dpp1_dscl_set_scaler_manual_scale() [all …]
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A D | dcn10_dpp.c | 134 struct scaler_data *scl_data, in dpp1_get_optimal_number_of_taps() argument 144 if (scl_data->viewport.width > scl_data->h_active && in dpp1_get_optimal_number_of_taps() 163 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps() 167 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps() 171 scl_data->taps.v_taps_c = 2; in dpp1_get_optimal_number_of_taps() 175 scl_data->taps.h_taps_c = 2; in dpp1_get_optimal_number_of_taps() 184 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps() 186 scl_data->taps.v_taps = 1; in dpp1_get_optimal_number_of_taps() 188 scl_data->taps.h_taps_c = 1; in dpp1_get_optimal_number_of_taps() 190 scl_data->taps.v_taps_c = 1; in dpp1_get_optimal_number_of_taps() [all …]
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A D | dcn10_hw_sequencer.c | 2716 &pipe_ctx->plane_res.scl_data.viewport, in dcn10_update_dchubp_dpp() 2717 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn10_update_dchubp_dpp() 3251 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dcn10_can_pipe_disable_cursor() local 3252 struct rect r1 = scl_data->recout, r2, r2_half; in dcn10_can_pipe_disable_cursor() 3267 r2 = test_pipe->plane_res.scl_data.recout; in dcn10_can_pipe_disable_cursor() 3279 r2_half = split_pipe->plane_res.scl_data.recout; in dcn10_can_pipe_disable_cursor() 3393 (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x; in dcn10_set_cursor_position() 3400 pipe_ctx->plane_res.scl_data.viewport.height; in dcn10_set_cursor_position() 3402 pipe_ctx->plane_res.scl_data.viewport.y; in dcn10_set_cursor_position() 3456 pipe_ctx->plane_res.scl_data.viewport.width; in dcn10_set_cursor_position() [all …]
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A D | dcn10_dpp.h | 1367 struct scaler_data scl_data; member 1398 const struct scaler_data *scl_data, 1490 const struct scaler_data *scl_data); 1511 struct scaler_data *scl_data,
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/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
A D | dcn30_dpp.c | 378 struct scaler_data *scl_data, in dpp3_get_optimal_number_of_taps() argument 386 if (scl_data->viewport.width > scl_data->h_active && in dpp3_get_optimal_number_of_taps() 398 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps() 400 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps() 407 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps() 414 scl_data->taps.v_taps_c = 4; in dpp3_get_optimal_number_of_taps() 419 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); in dpp3_get_optimal_number_of_taps() 421 scl_data->taps.h_taps_c = 4; in dpp3_get_optimal_number_of_taps() 465 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps() 467 scl_data->taps.v_taps = 1; in dpp3_get_optimal_number_of_taps() [all …]
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A D | dcn30_dpp.h | 573 struct scaler_data scl_data; member
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/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
A D | dce60_hw_sequencer.c | 202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color() 248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler() 266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler() 371 pipe_ctx->plane_res.scl_data.viewport.width, in dce60_program_front_end_for_pipe() 372 pipe_ctx->plane_res.scl_data.viewport.height, in dce60_program_front_end_for_pipe() 373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe() 374 pipe_ctx->plane_res.scl_data.viewport.y, in dce60_program_front_end_for_pipe() 375 pipe_ctx->plane_res.scl_data.recout.width, in dce60_program_front_end_for_pipe() 376 pipe_ctx->plane_res.scl_data.recout.height, in dce60_program_front_end_for_pipe() 377 pipe_ctx->plane_res.scl_data.recout.x, in dce60_program_front_end_for_pipe() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/core/ |
A D | dc_resource.c | 873 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios() 874 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios() 1126 &pipe_ctx->plane_res.scl_data, in resource_build_scaling_params() 1132 &pipe_ctx->plane_res.scl_data, in resource_build_scaling_params() 1153 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; in resource_build_scaling_params() 1155 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; in resource_build_scaling_params() 1176 pipe_ctx->plane_res.scl_data.viewport.x, in resource_build_scaling_params() 1180 pipe_ctx->plane_res.scl_data.recout.x, in resource_build_scaling_params() 1181 pipe_ctx->plane_res.scl_data.recout.y, in resource_build_scaling_params() 1182 pipe_ctx->plane_res.scl_data.h_active, in resource_build_scaling_params() [all …]
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A D | dc_hw_sequencer.c | 322 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color() 378 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
A D | dcn20_dpp.c | 270 const struct scaler_data *scl_data, in dscl2_calc_lb_num_partitions() argument 278 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions() 279 scl_data->viewport.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions() 280 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions() 281 scl_data->viewport_c.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions() 315 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
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A D | dcn20_hwseq.c | 1340 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn20_detect_pipe_changes() 1343 …if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(… in dcn20_detect_pipe_changes() 1344 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, in dcn20_detect_pipe_changes() 1345 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) in dcn20_detect_pipe_changes() 1486 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; in dcn20_update_dchubp_dpp() 1487 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); in dcn20_update_dchubp_dpp() 1490 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn20_update_dchubp_dpp() 1500 &pipe_ctx->plane_res.scl_data.viewport, in dcn20_update_dchubp_dpp() 1501 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn20_update_dchubp_dpp() 1545 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; in dcn20_update_dchubp_dpp()
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A D | dcn20_dpp.h | 693 struct scaler_data scl_data; member 746 const struct scaler_data *scl_data,
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A D | dcn20_resource.c | 1920 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm() 1937 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm() 2264 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; in dcn20_populate_dml_pipes_from_context() 2315 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context() 2320 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
A D | dce_transform.c | 1166 struct scaler_data *scl_data, in dce_transform_get_optimal_number_of_taps() argument 1174 (scl_data->viewport.width > scl_data->recout.width)) in dce_transform_get_optimal_number_of_taps() 1179 scl_data->lb_params.depth, in dce_transform_get_optimal_number_of_taps() 1195 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps() 1196 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps() 1197 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); in dce_transform_get_optimal_number_of_taps() 1198 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); in dce_transform_get_optimal_number_of_taps() 1204 && scl_data->taps.v_taps > 1) { in dce_transform_get_optimal_number_of_taps() 1208 if (scl_data->taps.v_taps <= 1) in dce_transform_get_optimal_number_of_taps() 1214 if (max_num_of_lines <= scl_data->taps.v_taps_c && scl_data->taps.v_taps_c > 1) { in dce_transform_get_optimal_number_of_taps() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/calcs/ |
A D | dcn_calcs.c | 404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params() 412 switch (pipe->plane_res.scl_data.lb_params.depth) { in pipe_ctx_to_e2e_pipe_params() 968 + pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth() 970 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth() 974 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth() 977 - pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth() 980 + pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth() 982 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth() 986 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth() 989 - pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth() [all …]
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A D | dce_calcs.c | 2827 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data() 2829 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data() 2830 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data() 2831 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data() 2886 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data() 2889 pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value); in populate_initial_data() 2891 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); in populate_initial_data() 2930 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data() 2932 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data() 2933 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
A D | dce110_transform_v.c | 50 const struct scaler_data *scl_data, in calculate_viewport() argument 55 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport() 56 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport() 58 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport() 60 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport() 66 if (scl_data->format == PIXEL_FORMAT_420BPP8) { in calculate_viewport()
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A D | dce110_hw_sequencer.c | 1438 pipe_ctx->plane_res.scl_data.lb_params.depth, 1456 &pipe_ctx->plane_res.scl_data); 2844 pipe_ctx->plane_res.scl_data.viewport.width, 2845 pipe_ctx->plane_res.scl_data.viewport.height, 2846 pipe_ctx->plane_res.scl_data.viewport.x, 2847 pipe_ctx->plane_res.scl_data.viewport.y, 2848 pipe_ctx->plane_res.scl_data.recout.width, 2849 pipe_ctx->plane_res.scl_data.recout.height, 2850 pipe_ctx->plane_res.scl_data.recout.x, 2851 pipe_ctx->plane_res.scl_data.recout.y); [all …]
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
A D | transform.h | 186 const struct scaler_data *scl_data); 195 struct scaler_data *scl_data, 300 const struct scaler_data *scl_data,
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A D | dpp.h | 160 const struct scaler_data *scl_data); 169 struct scaler_data *scl_data,
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
A D | amdgpu_dm_trace.h | 437 __entry->recout_x = plane_res->scl_data.recout.x; 438 __entry->recout_y = plane_res->scl_data.recout.y; 439 __entry->recout_w = plane_res->scl_data.recout.width; 440 __entry->recout_h = plane_res->scl_data.recout.height; 441 __entry->viewport_x = plane_res->scl_data.viewport.x; 442 __entry->viewport_y = plane_res->scl_data.viewport.y; 443 __entry->viewport_w = plane_res->scl_data.viewport.width; 444 __entry->viewport_h = plane_res->scl_data.viewport.height;
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/linux/drivers/gpu/drm/amd/display/dc/inc/ |
A D | core_types.h | 326 struct scaler_data scl_data; member
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/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
A D | dcn21_resource.c | 1246 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn21_fast_validate_bw() 1247 &pipe->plane_res.scl_data.recout, in dcn21_fast_validate_bw()
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