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Searched refs:set_drr (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_init.c61 .set_drr = dcn10_set_drr,
A Ddcn10_optc.c1562 .set_drr = optc1_set_drr,
A Ddcn10_hw_sequencer.c1018 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn10_reset_back_end_for_pipe()
1019 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn10_reset_back_end_for_pipe()
3046 pipe_ctx[i]->stream_res.tg->funcs->set_drr( in dcn10_set_drr()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_init.c62 .set_drr = dcn10_set_drr,
A Ddcn201_optc.c169 .set_drr = optc1_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_init.c62 .set_drr = dcn10_set_drr,
A Ddcn20_optc.c568 .set_drr = optc1_set_drr,
A Ddcn20_hwseq.c742 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn20_enable_stream_timing()
743 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn20_enable_stream_timing()
2231 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn20_reset_back_end_for_pipe()
2232 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn20_reset_back_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_init.c67 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_init.c65 .set_drr = dcn10_set_drr,
A Ddcn31_optc.c246 .set_drr = optc31_set_drr,
A Ddcn31_hwseq.c540 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn31_reset_back_end_for_pipe()
541 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn31_reset_back_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_init.c62 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_init.c62 .set_drr = dcn10_set_drr,
A Ddcn30_optc.c322 .set_drr = optc1_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_timing_generator.c211 .set_drr = dce110_timing_generator_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_timing_generator.c230 .set_drr = dce110_timing_generator_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dtiming_generator.h229 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); member
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dhw_sequencer.h120 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, member
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_hw_sequencer.c1585 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1586 pipe_ctx->stream_res.tg->funcs->set_drr(
1973 static void set_drr(struct pipe_ctx **pipe_ctx, function
1991 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
3094 .set_drr = set_drr,
A Ddce110_timing_generator.c2232 .set_drr =
/linux/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_timing_generator.c1192 .set_drr = dce120_timing_generator_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc.c424 dc->hwss.set_drr(&pipe, in dc_stream_adjust_vmin_vmax()

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