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Searched refs:set_parent (Results 1 – 25 of 112) sorted by relevance

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/linux/drivers/clk/
A Dclk-composite.c30 return mux_ops->set_parent(mux_hw, index); in clk_composite_set_parent()
84 mux_hw && mux_ops && mux_ops->set_parent) { in clk_composite_determine_rate()
190 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
192 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
270 if (mux_ops->set_parent) in __clk_hw_register_composite()
271 clk_composite_ops->set_parent = clk_composite_set_parent; in __clk_hw_register_composite()
305 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/linux/drivers/clk/actions/
A Dowl-composite.c147 .set_parent = owl_comp_set_parent,
164 .set_parent = owl_comp_set_parent,
193 .set_parent = owl_comp_set_parent,
A Dowl-mux.c58 .set_parent = owl_mux_set_parent,
/linux/drivers/clk/tegra/
A Dclk-tegra-super-cclk.c40 return tegra_clk_super_ops.set_parent(hw, index); in cclk_super_set_parent()
111 .set_parent = cclk_super_set_parent,
119 .set_parent = cclk_super_set_parent,
A Dclk-periph.c33 return mux_ops->set_parent(mux_hw, index); in clk_periph_set_parent()
131 .set_parent = clk_periph_set_parent,
144 .set_parent = clk_periph_set_parent,
154 .set_parent = clk_periph_set_parent,
A Dclk-super.c140 .set_parent = clk_super_set_parent,
193 .set_parent = clk_super_set_parent,
/linux/drivers/clk/ti/
A Ddpll.c38 .set_parent = &omap3_noncore_dpll_set_parent,
63 .set_parent = &omap3_noncore_dpll_set_parent,
76 .set_parent = &omap3_noncore_dpll_set_parent,
117 .set_parent = &omap3_noncore_dpll_set_parent,
129 .set_parent = &omap3_noncore_dpll_set_parent,
141 .set_parent = &omap3_noncore_dpll_set_parent,
/linux/drivers/clk/versatile/
A Dclk-sp810.c67 .set_parent = clk_sp810_timerclken_set_parent,
128 init.ops->set_parent(&sp810->timerclken[i].hw, 1); in clk_sp810_of_setup()
/linux/drivers/clk/pxa/
A Dclk-pxa.h24 .set_parent = dummy_clk_set_parent, \
75 .set_parent = name ## _set_parent, \
/linux/drivers/gpu/drm/mcde/
A Dmcde_clk_div.c44 unsigned long *prate, bool set_parent) in mcde_clk_div_choose_div() argument
55 if (set_parent) in mcde_clk_div_choose_div()
/linux/drivers/sh/clk/
A Dcore.c523 if (clk->ops->set_parent) in clk_set_parent()
524 ret = clk->ops->set_parent(clk, parent); in clk_set_parent()
580 if (likely(clkp->ops->set_parent)) in clks_core_resume()
581 clkp->ops->set_parent(clkp, in clks_core_resume()
/linux/drivers/clk/qcom/
A Dclk-rcg2.c440 .set_parent = clk_rcg2_set_parent,
453 .set_parent = clk_rcg2_set_parent,
582 .set_parent = clk_rcg2_set_parent,
640 .set_parent = clk_rcg2_set_parent,
710 .set_parent = clk_rcg2_set_parent,
800 .set_parent = clk_rcg2_set_parent,
905 .set_parent = clk_rcg2_set_parent,
1043 .set_parent = clk_rcg2_set_parent,
1306 .set_parent = clk_rcg2_set_parent,
A Dclk-rcg.c812 .set_parent = clk_rcg_set_parent,
823 .set_parent = clk_rcg_set_parent,
834 .set_parent = clk_rcg_set_parent,
846 .set_parent = clk_rcg_set_parent,
858 .set_parent = clk_rcg_set_parent,
870 .set_parent = clk_rcg_set_parent,
882 .set_parent = clk_dyn_rcg_set_parent,
A Dclk-regmap-mux.c54 .set_parent = mux_set_parent,
A Dkrait-cc.c43 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
52 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
/linux/drivers/clk/rockchip/
A Dclk-pll.c209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
442 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
691 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
727 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
/linux/drivers/clk/imx/
A Dclk-busy.c143 ret = busy->mux_ops->set_parent(&busy->mux.hw, index); in clk_busy_mux_set_parent()
152 .set_parent = clk_busy_mux_set_parent,
/linux/drivers/clk/mediatek/
A Dclk-mux.c122 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
131 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
/linux/sound/soc/codecs/
A Dtlv320aic32x4-clk.c271 .set_parent = clk_aic32x4_pll_set_parent,
295 .set_parent = clk_aic32x4_codec_clkin_set_parent,
382 .set_parent = clk_aic32x4_bdiv_set_parent,
/linux/drivers/clk/socfpga/
A Dclk-gate.c168 .set_parent = socfpga_clk_set_parent,
236 ops->set_parent = NULL; in socfpga_gate_init()
/linux/drivers/clk/sprd/
A Dcomposite.c54 .set_parent = sprd_comp_set_parent,
A Dmux.c73 .set_parent = sprd_mux_set_parent,
/linux/drivers/clk/at91/
A Dclk-i2s-mux.c47 .set_parent = clk_i2s_mux_set_parent,
/linux/drivers/clk/sunxi-ng/
A Dccu_mp.c242 .set_parent = ccu_mp_set_parent,
322 .set_parent = ccu_mp_set_parent,
/linux/drivers/clk/uniphier/
A Dclk-uniphier-mux.c52 .set_parent = uniphier_clk_mux_set_parent,

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