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Searched refs:set_rate (Results 1 – 25 of 266) sorted by relevance

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/linux/arch/arm/mach-omap1/
A Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
424 .set_rate = &omap1_set_uart_rate,
463 .set_rate = &omap1_set_uart_rate,
482 .set_rate = &omap1_set_uart_rate,
579 .set_rate = &omap1_set_ext_clk_rate,
597 .set_rate = &omap1_set_ext_clk_rate,
[all …]
/linux/drivers/clk/ti/
A Ddpll.c37 .set_rate = &omap3_noncore_dpll_set_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
116 .set_rate = &omap3_noncore_dpll_set_rate,
128 .set_rate = &omap3_dpll5_set_rate,
140 .set_rate = &omap3_dpll4_set_rate,
/linux/drivers/clk/actions/
A Dowl-composite.c157 .set_rate = owl_comp_div_set_rate,
174 .set_rate = owl_comp_fact_set_rate,
186 .set_rate = owl_comp_fix_fact_set_rate,
/linux/drivers/sh/clk/
A Dcpg.c182 .set_rate = sh_clk_div_set_rate,
188 .set_rate = sh_clk_div_set_rate,
315 .set_rate = sh_clk_div_set_rate,
367 .set_rate = sh_clk_div_set_rate,
447 .set_rate = fsidiv_set_rate,
A Dcore.c490 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
491 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
583 if (likely(clkp->ops->set_rate)) in clks_core_resume()
584 clkp->ops->set_rate(clkp, rate); in clks_core_resume()
/linux/drivers/clk/
A Dclk-composite.c169 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
189 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
193 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
291 if (rate_ops->set_rate) { in __clk_hw_register_composite()
293 clk_composite_ops->set_rate = in __clk_hw_register_composite()
305 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/linux/drivers/clk/mvebu/
A Dclk-corediv.c203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
/linux/drivers/clk/samsung/
A Dclk-pll.c297 .set_rate = samsung_pll35xx_set_rate,
408 .set_rate = samsung_pll36xx_set_rate,
492 .set_rate = samsung_pll0822x_set_rate,
588 .set_rate = samsung_pll0831x_set_rate,
713 .set_rate = samsung_pll45xx_set_rate,
858 .set_rate = samsung_pll46xx_set_rate,
1087 .set_rate = samsung_s3c2410_pll_set_rate,
1095 .set_rate = samsung_s3c2410_pll_set_rate,
1234 .set_rate = samsung_pll2550xx_set_rate,
1326 .set_rate = samsung_pll2650x_set_rate,
[all …]
/linux/drivers/clk/mxs/
A Dclk-div.c57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
/linux/arch/sh/kernel/cpu/sh4/
A Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/linux/drivers/clk/tegra/
A Dclk-periph.c69 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
134 .set_rate = clk_periph_set_rate,
157 .set_rate = clk_periph_set_rate,
A Dclk-tegra-super-cclk.c46 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
112 .set_rate = cclk_super_set_rate,
/linux/drivers/clk/ux500/
A Dclk-prcmu.c197 .set_rate = clk_prcmu_set_rate,
214 .set_rate = clk_prcmu_set_rate,
241 .set_rate = clk_prcmu_set_rate,
/linux/drivers/clk/qcom/
A Dclk-alpha-pll.c921 .set_rate = clk_alpha_pll_set_rate,
931 .set_rate = alpha_pll_huayra_set_rate,
941 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1036 .set_rate = clk_alpha_pll_postdiv_set_rate,
1277 .set_rate = alpha_pll_fabia_set_rate,
1372 .set_rate = clk_trion_pll_postdiv_set_rate,
1570 .set_rate = alpha_pll_trion_set_rate,
1581 .set_rate = alpha_pll_trion_set_rate,
1640 .set_rate = clk_alpha_pll_agera_set_rate,
1791 .set_rate = alpha_pll_lucid_5lpe_set_rate,
[all …]
A Dclk-rcg2.c443 .set_rate = clk_rcg2_set_rate,
456 .set_rate = clk_rcg2_set_floor_rate,
584 .set_rate = clk_edp_pixel_set_rate,
642 .set_rate = clk_byte_set_rate,
712 .set_rate = clk_byte2_set_rate,
802 .set_rate = clk_pixel_set_rate,
907 .set_rate = clk_gfx3d_set_rate,
1046 .set_rate = clk_rcg2_shared_set_rate,
1308 .set_rate = clk_rcg2_dp_set_rate,
A Dclk-rcg.c815 .set_rate = clk_rcg_set_rate,
826 .set_rate = clk_rcg_bypass_set_rate,
837 .set_rate = clk_rcg_bypass2_set_rate,
849 .set_rate = clk_rcg_pixel_set_rate,
861 .set_rate = clk_rcg_esc_set_rate,
873 .set_rate = clk_rcg_lcc_set_rate,
885 .set_rate = clk_dyn_rcg_set_rate,
/linux/drivers/clk/st/
A Dclk-flexgen.c184 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
185 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
187 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
188 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
202 .set_rate = flexgen_set_rate,
/linux/drivers/clk/imx/
A Dclk-pllv3.c155 .set_rate = clk_pllv3_set_rate,
210 .set_rate = clk_pllv3_sys_set_rate,
299 .set_rate = clk_pllv3_av_set_rate,
392 .set_rate = clk_pllv3_vf610_set_rate,
A Dclk-busy.c63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
73 .set_rate = clk_busy_divider_set_rate,
/linux/drivers/clk/baikal-t1/
A Dccu-div.c502 .set_rate = ccu_div_var_set_rate_fast,
509 .set_rate = ccu_div_var_set_rate_slow,
519 .set_rate = ccu_div_fixed_set_rate,
526 .set_rate = ccu_div_fixed_set_rate,
/linux/include/linux/phy/
A Dphy-dp.h73 u8 set_rate : 1; member
/linux/drivers/clk/at91/
A Dclk-usb.c181 .set_rate = at91sam9x5_clk_usb_set_rate,
219 .set_rate = at91sam9x5_clk_usb_set_rate,
388 .set_rate = at91rm9200_clk_usb_set_rate,
A Dclk-audio-pll.c432 .set_rate = clk_audio_pll_frac_set_rate,
440 .set_rate = clk_audio_pll_pad_set_rate,
448 .set_rate = clk_audio_pll_pmc_set_rate,
/linux/sound/soc/codecs/
A Dtlv320aic32x4-clk.c270 .set_rate = clk_aic32x4_pll_set_rate,
356 .set_rate = clk_aic32x4_div_set_rate,
384 .set_rate = clk_aic32x4_div_set_rate,
/linux/include/linux/qed/
A Dqed_iov_if.h28 int (*set_rate) (struct qed_dev *cdev, int vfid, member

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