Home
last modified time | relevance | path

Searched refs:set_rate_and_parent (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/clk/ti/
A Ddpll.c39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
118 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
130 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
142 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
/linux/drivers/clk/qcom/
A Dclk-rcg2.c444 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
457 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
585 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
643 .set_rate_and_parent = clk_byte_set_rate_and_parent,
713 .set_rate_and_parent = clk_byte2_set_rate_and_parent,
803 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
908 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
1047 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
1309 .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent,
A Dclk-rcg.c838 .set_rate_and_parent = clk_rcg_bypass2_set_rate_and_parent,
850 .set_rate_and_parent = clk_rcg_pixel_set_rate_and_parent,
862 .set_rate_and_parent = clk_rcg_esc_set_rate_and_parent,
886 .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
A Dclk-regmap-mux-div.c227 .set_rate_and_parent = mux_div_set_rate_and_parent,
/linux/drivers/clk/tegra/
A Dclk-tegra20-emc.c220 .set_rate_and_parent = emc_set_rate_and_parent,
/linux/drivers/clk/
A Dclk-composite.c306 clk_composite_ops->set_rate_and_parent = in __clk_hw_register_composite()
A Dclk.c2089 if (core->ops->set_rate_and_parent) { in clk_change_rate()
2091 core->ops->set_rate_and_parent(core->hw, core->new_rate, in clk_change_rate()
3465 if (core->ops->set_rate_and_parent && in __clk_core_init()
/linux/drivers/clk/mmp/
A Dclk-mix.c434 .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
/linux/Documentation/driver-api/
A Dclk.rst90 int (*set_rate_and_parent)(struct clk_hw *hw,
/linux/drivers/clk/microchip/
A Dclk-core.c553 .set_rate_and_parent = roclk_set_rate_and_parent,
/linux/include/linux/
A Dclk-provider.h241 int (*set_rate_and_parent)(struct clk_hw *hw, member

Completed in 29 milliseconds