| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_opp_csc_v.c | 119 set_reg_field_value( in program_color_matrix_v()
130 set_reg_field_value( in program_color_matrix_v()
136 set_reg_field_value( in program_color_matrix_v()
148 set_reg_field_value( in program_color_matrix_v()
154 set_reg_field_value( in program_color_matrix_v()
234 set_reg_field_value( in program_color_matrix_v()
348 set_reg_field_value( in program_color_matrix_v()
368 set_reg_field_value( in configure_graphics_mode_v()
497 set_reg_field_value( in set_Denormalization()
660 set_reg_field_value( in program_input_csc()
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| A D | dce110_opp_regamma_v.c | 44 set_reg_field_value( in power_on_lut()
50 set_reg_field_value( in power_on_lut()
57 set_reg_field_value( in power_on_lut()
63 set_reg_field_value( in power_on_lut()
93 set_reg_field_value( in set_bypass_input_gamma()
107 set_reg_field_value( in configure_regamma_mode()
139 set_reg_field_value( in regamma_config_regions_and_segments()
145 set_reg_field_value( in regamma_config_regions_and_segments()
156 set_reg_field_value( in regamma_config_regions_and_segments()
167 set_reg_field_value( in regamma_config_regions_and_segments()
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| A D | dce110_timing_generator.c | 134 set_reg_field_value( in dce110_timing_generator_enable_crtc()
159 set_reg_field_value( in dce110_timing_generator_program_blank_color()
164 set_reg_field_value( in dce110_timing_generator_program_blank_color()
169 set_reg_field_value( in dce110_timing_generator_program_blank_color()
620 set_reg_field_value( in dce110_timing_generator_program_blanking()
629 set_reg_field_value( in dce110_timing_generator_program_blanking()
641 set_reg_field_value( in dce110_timing_generator_program_blanking()
650 set_reg_field_value( in dce110_timing_generator_program_blanking()
663 set_reg_field_value( in dce110_timing_generator_program_blanking()
672 set_reg_field_value( in dce110_timing_generator_program_blanking()
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| A D | dce110_mem_input_v.c | 408 set_reg_field_value( in program_pixel_format()
413 set_reg_field_value( in program_pixel_format()
429 set_reg_field_value( in program_pixel_format()
460 set_reg_field_value( in program_pixel_format()
676 set_reg_field_value( in program_urgency_watermark()
682 set_reg_field_value( in program_urgency_watermark()
832 set_reg_field_value( in program_nbp_watermark()
841 set_reg_field_value( in program_nbp_watermark()
846 set_reg_field_value( in program_nbp_watermark()
851 set_reg_field_value( in program_nbp_watermark()
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| A D | dce110_transform_v.c | 91 set_reg_field_value( in program_viewport()
96 set_reg_field_value( in program_viewport()
105 set_reg_field_value( in program_viewport()
110 set_reg_field_value( in program_viewport()
121 set_reg_field_value( in program_viewport()
126 set_reg_field_value( in program_viewport()
135 set_reg_field_value( in program_viewport()
140 set_reg_field_value( in program_viewport()
192 set_reg_field_value( in setup_scaling_configuration()
197 set_reg_field_value( in setup_scaling_configuration()
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| A D | dce110_timing_generator_v.c | 104 set_reg_field_value( in dce110_timing_generator_v_blank_crtc()
110 set_reg_field_value( in dce110_timing_generator_v_blank_crtc()
124 set_reg_field_value( in dce110_timing_generator_v_unblank_crtc()
130 set_reg_field_value( in dce110_timing_generator_v_unblank_crtc()
260 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
269 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
282 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
291 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
304 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
313 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
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| A D | dce110_compressor.c | 150 set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); in dce110_compressor_power_up_fbc()
154 set_reg_field_value( in dce110_compressor_power_up_fbc()
164 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); in dce110_compressor_power_up_fbc()
166 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN); in dce110_compressor_power_up_fbc()
204 set_reg_field_value( in dce110_compressor_enable_fbc()
224 set_reg_field_value(misc_value, 1, in dce110_compressor_enable_fbc()
226 set_reg_field_value(misc_value, 1, in dce110_compressor_enable_fbc()
228 set_reg_field_value(misc_value, 0x14, in dce110_compressor_enable_fbc()
337 set_reg_field_value( in dce110_compressor_program_compressed_surface_address_and_pitch()
356 set_reg_field_value( in dce110_compressor_set_fbc_invalidation_triggers()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_audio.c | 359 set_reg_field_value(value, 1, in dce_aud_az_enable()
430 set_reg_field_value(value, in dce_aud_az_configure()
441 set_reg_field_value(value, in dce_aud_az_configure()
449 set_reg_field_value(value, in dce_aud_az_configure()
454 set_reg_field_value(value, in dce_aud_az_configure()
465 set_reg_field_value(value, in dce_aud_az_configure()
473 set_reg_field_value(value, in dce_aud_az_configure()
483 set_reg_field_value(value, in dce_aud_az_configure()
552 set_reg_field_value(value, in dce_aud_az_configure()
557 set_reg_field_value(value, in dce_aud_az_configure()
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| A D | dce_link_encoder.c | 636 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); in aux_initialize()
637 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); in aux_initialize()
644 set_reg_field_value(value, 1, in aux_initialize()
1653 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_enable_hpd()
1663 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_disable_hpd()
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| A D | dce_aux.c | 128 set_reg_field_value( in acquire_engine()
136 set_reg_field_value( in acquire_engine()
151 set_reg_field_value( in acquire_engine()
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| /linux/drivers/gpu/drm/amd/display/dc/dce112/ |
| A D | dce112_compressor.c | 122 set_reg_field_value( in lpt_memory_control_config()
129 set_reg_field_value( in lpt_memory_control_config()
153 set_reg_field_value( in lpt_memory_control_config()
331 set_reg_field_value( in dce112_compressor_power_up_fbc()
534 set_reg_field_value( in dce112_compressor_program_compressed_surface_address_and_pitch()
569 set_reg_field_value( in dce112_compressor_disable_lpt()
579 set_reg_field_value( in dce112_compressor_disable_lpt()
589 set_reg_field_value( in dce112_compressor_disable_lpt()
608 set_reg_field_value( in dce112_compressor_enable_lpt()
619 set_reg_field_value( in dce112_compressor_enable_lpt()
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| A D | dce112_hw_sequencer.c | 91 set_reg_field_value( in dce112_init_pte()
97 set_reg_field_value( in dce112_init_pte()
103 set_reg_field_value( in dce112_init_pte()
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| /linux/drivers/gpu/drm/amd/display/dc/dce80/ |
| A D | dce80_timing_generator.c | 99 set_reg_field_value( in program_pix_dur()
133 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
139 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
147 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
152 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
158 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
163 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
170 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
176 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_timing_generator.c | 99 set_reg_field_value( in program_pix_dur()
139 set_reg_field_value( in dce60_timing_generator_enable_advanced_request()
144 set_reg_field_value( in dce60_timing_generator_enable_advanced_request()
150 set_reg_field_value( in dce60_timing_generator_enable_advanced_request()
155 set_reg_field_value( in dce60_timing_generator_enable_advanced_request()
162 set_reg_field_value( in dce60_timing_generator_enable_advanced_request()
168 set_reg_field_value( in dce60_timing_generator_enable_advanced_request()
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| /linux/drivers/gpu/drm/amd/display/dc/dce120/ |
| A D | dce120_hw_sequencer.c | 127 set_reg_field_value(
133 set_reg_field_value(
139 set_reg_field_value(
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| A D | dce120_timing_generator.c | 418 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); in dce120_timing_generator_disable_vga()
419 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); in dce120_timing_generator_disable_vga()
420 set_reg_field_value( in dce120_timing_generator_disable_vga()
422 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); in dce120_timing_generator_disable_vga()
635 set_reg_field_value( in dce120_timing_generator_enable_advanced_request()
647 set_reg_field_value( in dce120_timing_generator_enable_advanced_request()
936 set_reg_field_value( in dce120_timing_generator_set_test_pattern()
946 set_reg_field_value( in dce120_timing_generator_set_test_pattern()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce80/ |
| A D | irq_service_dce80.c | 58 set_reg_field_value( in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| A D | irq_service_dce120.c | 58 set_reg_field_value( in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 67 set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce60/ |
| A D | irq_service_dce60.c | 65 set_reg_field_value( in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_services.h | 111 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ macro
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 102 set_reg_field_value( in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| A D | irq_service_dce110.c | 57 set_reg_field_value(value, current_status ? 0 : 1, in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| A D | irq_service_dcn10.c | 151 set_reg_field_value( in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 176 set_reg_field_value( in hpd_ack()
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