| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | nv.c | 418 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
423 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
424 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
428 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
436 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
439 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
448 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
463 se_num, sh_num, reg_offset); in nv_read_register()
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| A D | soc15.c | 435 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register() argument
440 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
441 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
445 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
453 u32 sh_num, u32 reg_offset) in soc15_get_register_value() argument
456 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
467 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register() argument
482 se_num, sh_num, reg_offset); in soc15_read_register()
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| A D | gfx_v9_0.h | 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
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| A D | cik.c | 1124 u32 sh_num, u32 reg_offset) in cik_get_register_value() argument
1129 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1219 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register() argument
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
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| A D | vi.c | 745 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
750 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
764 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
765 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
769 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
840 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
851 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
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| A D | si.c | 1166 u32 sh_num, u32 reg_offset) in si_get_register_value() argument
1171 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1240 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register() argument
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
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| A D | amdgpu_kms.c | 760 unsigned sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
770 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
771 sh_num = 0xffffffff; in amdgpu_info_ioctl()
772 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) in amdgpu_info_ioctl()
785 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
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| A D | gfx_v9_4.c | 94 u32 sh_num, u32 instance) in gfx_v9_4_select_se_sh() argument
111 if (sh_num == 0xffffffff) in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
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| A D | amdgpu_gfx.h | 224 u32 sh_num, u32 instance);
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| A D | gfx_v6_0.c | 1302 u32 sh_num, u32 instance) in gfx_v6_0_select_se_sh() argument
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1316 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1317 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1321 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
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| A D | gfx_v9_4_2.c | 847 u32 sh_num, u32 instance) in gfx_v9_4_2_select_se_sh() argument
864 if (sh_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
868 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
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| A D | gfx_v7_0.c | 1589 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh() argument
1598 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1603 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1604 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1608 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
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| A D | amdgpu.h | 644 u32 sh_num, u32 reg_offset, u32 *value);
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| A D | gfx_v9_0.c | 2489 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2504 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
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| A D | gfx_v8_0.c | 3440 u32 se_num, u32 sh_num, u32 instance) in gfx_v8_0_select_se_sh() argument
3454 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3457 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
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| A D | gfx_v10_0.c | 3577 u32 sh_num, u32 instance);
4994 u32 sh_num, u32 instance) in gfx_v10_0_select_se_sh() argument
5011 if (sh_num == 0xffffffff) in gfx_v10_0_select_se_sh()
5015 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
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| /linux/drivers/gpu/drm/radeon/ |
| A D | si.c | 2947 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2951 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2954 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in si_select_se_sh()
2955 else if (sh_num == 0xffffffff) in si_select_se_sh()
2958 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
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| A D | cik.c | 3027 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3031 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3034 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in cik_select_se_sh()
3035 else if (sh_num == 0xffffffff) in cik_select_se_sh()
3038 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()
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