| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dpp_cm.c | 118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
213 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
215 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
269 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
273 reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; in dpp1_cm_get_reg_field()
277 reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field()
296 reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
304 reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_degamma_reg_field()
469 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp1_program_input_csc()
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| A D | dcn10_cm_common.h | 70 struct xfer_func_shift shifts; member
85 struct cm_color_matrix_shift shifts; member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dwb_cm.c | 52 reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
54 reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
57 reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
59 reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
61 reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
66 reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
68 reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
70 reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
74 reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B; in dwb3_get_reg_field_ogam()
315 gam_regs.shifts.csc_c11 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C11; in dwb3_program_gamut_remap()
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| A D | dcn30_dpp_cm.c | 179 reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
181 reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
184 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
186 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
188 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
193 reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
195 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
197 reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
201 reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
347 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
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| A D | dcn30_mpc.c | 181 reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
184 reg->shifts.exp_region0_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
193 reg->shifts.field_region_end = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
197 reg->shifts.field_region_end_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field()
201 reg->shifts.exp_region_start = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; in mpc3_ogam_get_reg_field()
1083 gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in program_gamut_remap()
1085 gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
1255 ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; in mpc3_set_output_csc()
1257 ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; in mpc3_set_output_csc()
1297 ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; in mpc3_set_ocsc_default()
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| A D | dcn30_dpp.c | 101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
643 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
645 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field()
647 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
649 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn3_dpp_cm_get_reg_field()
652 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
654 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
656 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
658 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_i2c_hw.c | 41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
623 const struct dce_i2c_shift *shifts, in dce_i2c_hw_construct() argument
630 dce_i2c_hw->shifts = shifts; in dce_i2c_hw_construct()
646 const struct dce_i2c_shift *shifts, in dce100_i2c_hw_construct() argument
653 shifts, in dce100_i2c_hw_construct()
663 const struct dce_i2c_shift *shifts, in dce112_i2c_hw_construct() argument
670 shifts, in dce112_i2c_hw_construct()
680 const struct dce_i2c_shift *shifts, in dcn1_i2c_hw_construct() argument
687 shifts, in dcn1_i2c_hw_construct()
697 const struct dce_i2c_shift *shifts, in dcn2_i2c_hw_construct() argument
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| A D | dce_i2c_hw.h | 291 const struct dce_i2c_shift *shifts; member
300 const struct dce_i2c_shift *shifts,
308 const struct dce_i2c_shift *shifts,
316 const struct dce_i2c_shift *shifts,
324 const struct dce_i2c_shift *shifts,
332 const struct dce_i2c_shift *shifts,
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| A D | dce_audio.h | 141 const struct dce_audio_shift *shifts; member
149 const struct dce_audio_shift *shifts,
157 const struct dce_audio_shift *shifts,
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| A D | dce_audio.c | 46 aud->shifts->field_name, aud->masks->field_name
1048 const struct dce_audio_shift *shifts, in dce_audio_create() argument
1064 audio->shifts = shifts; in dce_audio_create()
1074 const struct dce_audio_shift *shifts, in dce60_audio_create() argument
1090 audio->shifts = shifts; in dce60_audio_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_mpc.c | 164 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_output_csc()
166 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_output_csc()
222 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
224 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
250 reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
252 reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
254 reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
258 reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
260 reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
262 reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field()
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| A D | dcn20_dpp_cm.c | 189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
284 icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; in dpp2_program_input_csc()
286 icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; in dpp2_program_input_csc()
362 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
364 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
366 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
371 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
373 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
375 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
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| /linux/drivers/net/dsa/microchip/ |
| A D | ksz8795.c | 517 const u8 *shifts; in ksz8_r_dyn_mac_table() local
524 shifts = ksz8->shifts; in ksz8_r_dyn_mac_table()
581 const u8 *shifts; in ksz8_r_sta_mac_table() local
585 shifts = ksz8->shifts; in ksz8_r_sta_mac_table()
620 const u8 *shifts; in ksz8_w_sta_mac_table() local
624 shifts = ksz8->shifts; in ksz8_w_sta_mac_table()
652 const u8 *shifts; in ksz8_from_vlan() local
655 shifts = ksz8->shifts; in ksz8_from_vlan()
668 const u8 *shifts; in ksz8_to_vlan() local
671 shifts = ksz8->shifts; in ksz8_to_vlan()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_hubbub.c | 38 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 hubbub1->shifts->field_name, hubbub1->masks->field_name
77 hubbub3->shifts = hubbub_shift; in hubbub301_construct()
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| A D | dcn301_hwseq.c | 40 hws->shifts->field_name, hws->masks->field_name
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_hubbub.c | 41 hubbub1->shifts->field_name, hubbub1->masks->field_name
51 hubbub1->shifts->field_name, hubbub1->masks->field_name
102 hubbub->shifts = hubbub_shift; in hubbub201_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| A D | hw_factory_dcn10.c | 156 generic->shifts = &generic_shift[en]; in define_generic_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
191 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| A D | hw_factory_dcn21.c | 164 generic->shifts = &generic_shift[en]; in define_generic_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
199 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| A D | hw_factory_dcn20.c | 199 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
209 hpd->shifts = &hpd_shift; in define_hpd_registers()
219 generic->shifts = &generic_shift[en]; in define_generic_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| A D | hw_factory_dcn30.c | 192 generic->shifts = &generic_shift[en]; in define_generic_registers()
217 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
227 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| A D | hw_factory_dce110.c | 132 ddc->shifts = &ddc_shift; in define_ddc_registers()
142 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| A D | hw_factory_dce60.c | 136 ddc->shifts = &ddc_shift; in define_ddc_registers()
146 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| A D | hw_factory_dce80.c | 136 ddc->shifts = &ddc_shift; in define_ddc_registers()
146 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| A D | hw_factory_dce120.c | 149 ddc->shifts = &ddc_shift; in define_ddc_registers()
159 hpd->shifts = &hpd_shift; in define_hpd_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| A D | hw_ddc.h | 34 const struct ddc_sh_mask *shifts; member
|