Home
last modified time | relevance | path

Searched refs:sseu (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
A Dintel_sseu.c17 sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); in intel_sseu_set_info()
150 sseu->eu_total = compute_eu_total(sseu); in gen11_compute_sseu_info()
155 struct sseu_dev_info *sseu = &gt->info.sseu; in gen12_sseu_info_init() local
211 struct sseu_dev_info *sseu = &gt->info.sseu; in gen11_sseu_info_init() local
239 struct sseu_dev_info *sseu = &gt->info.sseu; in cherryview_sseu_info_init() local
272 sseu->eu_total = compute_eu_total(sseu); in cherryview_sseu_info_init()
296 struct sseu_dev_info *sseu = &gt->info.sseu; in gen9_sseu_info_init() local
355 sseu->eu_total = compute_eu_total(sseu); in gen9_sseu_info_init()
381 sseu->has_eu_pg = sseu->eu_per_subslice > 2; in gen9_sseu_info_init()
465 sseu->eu_total = compute_eu_total(sseu); in bdw_sseu_info_init()
[all …]
A Dintel_sseu_debugfs.c16 memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); in sseu_copy_subslices()
40 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
46 sseu->eu_total += eu_cnt; in cherryview_sseu_device_status()
92 sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask); in gen11_sseu_device_status()
185 if (sseu->slice_mask) { in bdw_sseu_device_status()
186 sseu->eu_per_subslice = info->sseu.eu_per_subslice; in bdw_sseu_device_status()
190 sseu->eu_total = sseu->eu_per_subslice * in bdw_sseu_device_status()
211 sseu->slice_mask); in i915_print_sseu_info()
221 sseu->eu_total); in i915_print_sseu_info()
258 memset(&sseu, 0, sizeof(sseu)); in intel_sseu_status()
[all …]
A Dintel_sseu.h67 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) in intel_sseu_from_device_info() argument
70 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
71 .subslice_mask = sseu->subslice_mask[0], in intel_sseu_from_device_info()
72 .min_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
73 .max_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
86 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
87 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
90 GEM_BUG_ON(ss_idx >= sseu->ss_stride); in intel_sseu_has_subslice()
92 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; in intel_sseu_has_subslice()
101 intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
[all …]
A Dintel_context_sseu.c17 const struct intel_sseu sseu) in gen8_emit_rpcs_config() argument
32 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
40 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
65 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
75 const struct intel_sseu sseu) in intel_context_reconfigure_sseu() argument
86 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
89 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
91 ce->sseu = sseu; in intel_context_reconfigure_sseu()
A Dintel_workarounds.c430 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
439 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
985 const struct sseu_dev_info *sseu = &gt->info.sseu; in icl_wa_init_mcr() local
989 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1001 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); in icl_wa_init_mcr()
1017 const struct sseu_dev_info *sseu = &gt->info.sseu; in xehp_init_mcr() local
1050 dss_mask = intel_sseu_get_subslices(sseu, 0); in xehp_init_mcr()
A Dintel_gt_types.h197 struct sseu_dev_info sseu; member
A Dintel_engine_cs.c841 engine->sseu = in engine_setup_common()
842 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
1222 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; in intel_engine_get_instdone() local
1248 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { in intel_engine_get_instdone()
1257 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { in intel_engine_get_instdone()
1268 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) in intel_engine_get_instdone()
A Dintel_context_types.h159 struct intel_sseu sseu; member
A Dintel_context.c384 ce->sseu = engine->sseu; in intel_context_init()
A Dintel_gt.c115 u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0); in slicemask()
908 intel_sseu_dump(&info->sseu, p); in intel_gt_info_print()
A Dintel_context.h45 const struct intel_sseu sseu);
A Dintel_engine_types.h304 struct intel_sseu sseu; member
A Dintel_lrc.c1287 intel_sseu_make_rpcs(engine->gt, &ce->sseu); in lrc_update_regs()
A Dintel_rps.c1115 switch (gt->info.sseu.eu_total) { in chv_rps_max_freq()
/linux/drivers/gpu/drm/i915/
A Di915_query.c34 const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu; in query_topology_info() local
42 if (sseu->max_slices == 0) in query_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in query_topology_info()
48 subslice_length = sseu->max_slices * sseu->ss_stride; in query_topology_info()
49 eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride; in query_topology_info()
62 topo.max_slices = sseu->max_slices; in query_topology_info()
63 topo.max_subslices = sseu->max_subslices; in query_topology_info()
67 topo.subslice_stride = sseu->ss_stride; in query_topology_info()
69 topo.eu_stride = sseu->eu_stride; in query_topology_info()
76 &sseu->slice_mask, slice_length)) in query_topology_info()
[all …]
A Di915_getparam.c16 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; in i915_getparam_ioctl() local
74 value = intel_sseu_subslice_total(sseu); in i915_getparam_ioctl()
79 value = sseu->eu_total; in i915_getparam_ioctl()
96 value = sseu->min_eu_in_pool; in i915_getparam_ioctl()
149 value = sseu->slice_mask; in i915_getparam_ioctl()
155 memcpy(&value, sseu->subslice_mask, in i915_getparam_ioctl()
156 min(sseu->ss_stride, (u8)sizeof(value))); in i915_getparam_ioctl()
A Di915_gpu_error.c431 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; in error_print_instdone() local
449 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) in error_print_instdone()
454 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) in error_print_instdone()
459 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) in error_print_instdone()
464 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) in error_print_instdone()
474 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) in error_print_instdone()
708 intel_sseu_print_topology(&gt->info.sseu, &p); in err_print_gt_info()
A Di915_perf_types.h417 struct intel_sseu sseu; member
A Di915_perf.c360 struct intel_sseu sseu; member
2260 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); in gen8_configure_context()
2404 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); in oa_configure_all_contexts()
2804 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; in get_default_sseu_config()
2965 perf->sseu = props->sseu; in i915_oa_stream_init()
3473 get_default_sseu_config(&props->sseu, props->engine); in i915_perf_open_ioctl_locked()
3710 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu); in read_properties_unlocked()
/linux/drivers/gpu/drm/i915/gem/
A Di915_gem_context.c788 struct intel_sseu *sseu; in set_proto_ctx_sseu() local
823 sseu = &pe->sseu; in set_proto_ctx_sseu()
833 sseu = &pc->legacy_rcs_sseu; in set_proto_ctx_sseu()
928 struct intel_sseu sseu) in intel_context_set_gem() argument
955 ret = intel_context_reconfigure_sseu(ce, sseu); in intel_context_set_gem()
1058 struct intel_sseu sseu = {}; in default_engines() local
1077 sseu = rcs_sseu; in default_engines()
1079 ret = intel_context_set_gem(ce, ctx, sseu); in default_engines()
1924 struct intel_sseu sseu; in set_sseu() local
1962 ret = intel_context_reconfigure_sseu(ce, sseu); in set_sseu()
[all …]
A Di915_gem_context_types.h125 struct intel_sseu sseu; member
/linux/drivers/gpu/drm/i915/gem/selftests/
A Di915_gem_context.c1143 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1184 struct intel_sseu sseu) in __sseu_test() argument
1195 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1200 hweight32(sseu.slice_mask), spin); in __sseu_test()
1245 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1248 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1255 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1258 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1262 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1276 ret = __sseu_test(name, flags, ce, obj, engine->sseu); in __igt_ctx_sseu()
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_ads.c513 hweight8(gt->info.sseu.slice_mask); in __guc_ads_init()

Completed in 70 milliseconds