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Searched refs:subslice (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
A Dintel_sseu.h81 int subslice) in intel_sseu_has_subslice() argument
84 int ss_idx = subslice / BITS_PER_BYTE; in intel_sseu_has_subslice()
87 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
94 return mask & BIT(subslice % BITS_PER_BYTE); in intel_sseu_has_subslice()
A Dintel_engine_cs.c1211 int slice, int subslice, i915_reg_t reg) in read_subslice_reg() argument
1214 slice, subslice); in read_subslice_reg()
1226 int subslice; in intel_engine_get_instdone() local
1249 instdone->sampler[slice][subslice] = in intel_engine_get_instdone()
1250 read_subslice_reg(engine, slice, subslice, in intel_engine_get_instdone()
1252 instdone->row[slice][subslice] = in intel_engine_get_instdone()
1253 read_subslice_reg(engine, slice, subslice, in intel_engine_get_instdone()
1258 instdone->sampler[slice][subslice] = in intel_engine_get_instdone()
1259 read_subslice_reg(engine, slice, subslice, in intel_engine_get_instdone()
1261 instdone->row[slice][subslice] = in intel_engine_get_instdone()
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A Dintel_workarounds.c964 unsigned int slice, unsigned int subslice) in __set_mcr_steering() argument
968 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); in __set_mcr_steering()
975 unsigned int slice, unsigned int subslice) in __add_mcr_wa() argument
986 unsigned int slice, subslice; in icl_wa_init_mcr() local
1001 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); in icl_wa_init_mcr()
1008 if (gt->info.l3bank_mask & BIT(subslice)) in icl_wa_init_mcr()
1011 __add_mcr_wa(gt, wal, slice, subslice); in icl_wa_init_mcr()
1018 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr() local
1076 subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE)); in xehp_init_mcr()
1077 WARN_ON(subslice > GEN_DSS_PER_GSLICE); in xehp_init_mcr()
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A Dintel_sseu.c63 int subslice) in sseu_eu_idx() argument
67 return slice * slice_stride + subslice * sseu->eu_stride; in sseu_eu_idx()
71 int subslice) in sseu_get_eus() argument
73 int i, offset = sseu_eu_idx(sseu, slice, subslice); in sseu_get_eus()
83 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, in sseu_set_eus() argument
86 int i, offset = sseu_eu_idx(sseu, slice, subslice); in sseu_set_eus()
/linux/drivers/gpu/drm/i915/
A Di915_gpu_error.c433 int subslice; in error_print_instdone() local
451 slice, subslice, in error_print_instdone()
452 ee->instdone.sampler[slice][subslice]); in error_print_instdone()
456 slice, subslice, in error_print_instdone()
457 ee->instdone.row[slice][subslice]); in error_print_instdone()
461 slice, subslice, in error_print_instdone()
462 ee->instdone.sampler[slice][subslice]); in error_print_instdone()
466 slice, subslice, in error_print_instdone()
467 ee->instdone.row[slice][subslice]); in error_print_instdone()
476 slice, subslice, in error_print_instdone()
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A Dintel_uncore.h213 int slice, int subslice);
215 i915_reg_t reg, int slice, int subslice);
A Dintel_uncore.c2530 int slice, int subslice) in intel_uncore_read_with_mcr_steering_fw() argument
2538 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); in intel_uncore_read_with_mcr_steering_fw()
2541 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); in intel_uncore_read_with_mcr_steering_fw()
2561 i915_reg_t reg, int slice, int subslice) in intel_uncore_read_with_mcr_steering() argument
2575 val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice, subslice); in intel_uncore_read_with_mcr_steering()
A Di915_reg.h2723 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) argument
2727 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) argument
9532 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) argument

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