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Searched refs:tcr_el1 (Results 1 – 7 of 7) sorted by relevance

/linux/tools/testing/selftests/kvm/lib/aarch64/
A Dprocessor.c218 uint64_t sctlr_el1, tcr_el1; in aarch64_vcpu_setup() local
248 tcr_el1 |= 1ul << 14; /* TG0 = 64KB */ in aarch64_vcpu_setup()
249 tcr_el1 |= 6ul << 32; /* IPS = 52 bits */ in aarch64_vcpu_setup()
252 tcr_el1 |= 0ul << 14; /* TG0 = 4KB */ in aarch64_vcpu_setup()
253 tcr_el1 |= 5ul << 32; /* IPS = 48 bits */ in aarch64_vcpu_setup()
256 tcr_el1 |= 1ul << 14; /* TG0 = 64KB */ in aarch64_vcpu_setup()
257 tcr_el1 |= 5ul << 32; /* IPS = 48 bits */ in aarch64_vcpu_setup()
260 tcr_el1 |= 0ul << 14; /* TG0 = 4KB */ in aarch64_vcpu_setup()
261 tcr_el1 |= 2ul << 32; /* IPS = 40 bits */ in aarch64_vcpu_setup()
264 tcr_el1 |= 1ul << 14; /* TG0 = 64KB */ in aarch64_vcpu_setup()
[all …]
/linux/arch/arm64/mm/
A Dproc.S83 mrs x7, tcr_el1
130 mrs x7, tcr_el1
133 msr tcr_el1, x8
493 msr tcr_el1, tcr
/linux/arch/arm64/include/asm/
A Dmmu_context.h71 unsigned long tcr = read_sysreg(tcr_el1); in __cpu_set_tcr_t0sz()
78 write_sysreg(tcr, tcr_el1); in __cpu_set_tcr_t0sz()
/linux/arch/arm64/kernel/
A Dcrash_core.c16 return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; in get_tcr_el1_t1sz()
A Dhyp-stub.S126 msr tcr_el1, x0
A Dcpufeature.c1622 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; in __cpu_enable_hw_dbm()
1624 write_sysreg(tcr, tcr_el1); in __cpu_enable_hw_dbm()
1840 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); in cpu_enable_e0pd()
/linux/arch/arm64/kvm/
A Darm.c1497 tcr = (read_sysreg(tcr_el1) & TCR_EL2_MASK) | TCR_EL2_RES1; in cpu_prepare_hyp_mode()

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